| /external/llvm/test/MC/ARM/ |
| neon-pairwise-encoding.s | 9 @ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3]
10 vpadd.f32 d16, d16, d17
18 @ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3]
19 vpadd.f32 d16, d17
81 @ CHECK: vpmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf3]
82 vpmin.f32 d16, d16, d17
95 @ CHECK: vpmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf3]
96 vpmax.f32 d16, d16, d17
|
| neont2-mul-accum-encoding.s | 8 vmla.f32 d16, d18, d17
12 vmla.f32 q9, q8, q10
18 @ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0d]
22 @ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0x40,0xef,0xf4,0x2d]
61 vmls.f32 d16, d18, d17
65 vmls.f32 q9, q8, q10
71 @ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0d]
75 @ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0x60,0xef,0xf4,0x2d]
|
| neon-absdiff-encoding.s | 15 @ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf3]
16 vabd.f32 d16, d16, d17
29 @ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf3]
30 vabd.f32 q8, q8, q9
|
| neont2-absdiff-encoding.s | 11 vabd.f32 d16, d16, d17
18 vabd.f32 q8, q8, q9
26 @ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0d]
33 @ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0d]
|
| neont2-mul-encoding.s | 8 vmul.f32 d16, d16, d17
12 vmul.f32 q8, q8, q9
20 @ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x0d]
24 @ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x0d]
|
| neon-sub-encoding.s | 7 vsub.f32 d16, d16, d17
12 vsub.f32 q8, q8, q9
18 vsub.f32 d17, d25
23 vsub.f32 q5, q6
29 @ CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2]
34 @ CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2]
40 @ CHECK: vsub.f32 d17, d17, d25 @ encoding: [0xa9,0x1d,0x61,0xf2]
45 @ CHECK: vsub.f32 q5, q5, q6 @ encoding: [0x4c,0xad,0x2a,0xf2]
|
| neon-bitwise-encoding.s | 88 veor.f32 q4, q7, q3
147 vand.f32 d4, d7, d3
205 vorr.f32 q4, q7, q3
283 vacge.f32 d5, d30
284 vacge.f32 q5, q3
286 vacgt.f32 d5, d30
287 vacgt.f32 q5, q3
290 @ vacle.f32 d5, d30
291 @ vacle.f32 q5, q3
292 @ vaclt.f32 d5, d3
[all...] |
| vpush-vpop.s | 13 vpop.f32 {d8, d9, d10, d11, d12}
|
| neont2-add-encoding.s | 13 @ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x0d]
14 vadd.f32 d16, d16, d17
15 @ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x0d]
16 vadd.f32 q8, q8, q9
|
| neon-vst-encoding.s | 77 vst3.f32 {d1, d2, d3}, [r6]!
118 vst4.f32 {d16, d17, d18, d19}, [r3:64], r5
147 vst2.f32 {d17[0], d19[0]}, [r0:64]
192 vst3.f32 {d1[1], d2[1], d3[1]}, [r6]!
227 vst4.f32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5
257 vst1.f32 {q2}, [r2]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
54 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
56 setOperationAction(ISD::FSUB, MVT::f32, Expand);
61 setOperationAction(ISD::FPOW, MVT::f32, Custom);
65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
69 setOperationAction(ISD::SETCC, MVT::f32, Expand);
73 setOperationAction(ISD::SELECT, MVT::f32, Custom);
377 DL, MVT::f32, SDValue(interp, 0));
382 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32)
[all...] |
| AMDILISelLowering.cpp | 47 (int)MVT::f32,
70 (int)MVT::f32,
210 setOperationAction(ISD::ConstantFP , MVT::f32 , Legal);
233 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
243 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
406 FLTTY = MVT::f32;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 51 LocVT == MVT::f32) {
107 LocVT == MVT::f32) {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 211 if (VA.getLocVT() == MVT::f32)
212 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
269 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
517 if (VA.getLocVT() != MVT::f32) {
695 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
699 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
703 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
729 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
734 setOperationAction(ISD::SELECT, MVT::f32, Expand);
737 setOperationAction(ISD::SETCC, MVT::f32, Expand)
[all...] |
| /external/openssl/crypto/bn/asm/ |
| ia64.S | 135 // (f32-f128) FP register bank over process context switch, thus
141 // programs for that matter) with -mfixed-range=f32-f127 command
332 { .mfi; (p16) ldf8 f32=[r15],8
370 { .mfi; (p16) ldf8 f32=[r33],8
437 { .mfi; (p16) ldf8 f32=[r15],8 // *(ap++)
500 { .mfi; (p16) ldf8 f32=[r33],8
636 ldf8 f32=[r33],32 };;
658 xma.hu f41=f32,f120,f0 }
659 { .mfi; xma.lu f40=f32,f120,f0 };; // (*)
660 { .mfi; xma.hu f51=f32,f121,f0
[all...] |
| /external/valgrind/main/none/tests/arm/ |
| neon64.stdout.exp | 22 vmov.f32 d0, #0.328125 :: Qd 0x3ea80000 0x3ea80000
23 vmov.f32 d0, #0.328125 :: Qd 0x3ea80000 0x3ea80000
24 vmov.f32 d0, #-0.328125 :: Qd 0xbea80000 0xbea80000
25 vmov.f32 d0, #-0.328125 :: Qd 0xbea80000 0xbea80000
[all...] |
| /external/clang/test/CodeGen/ |
| arm-arguments.c | 172 void f32(struct s32 s) { } function
173 // AAPCS: @f32([1 x i64] %s.coerce)
174 // APCS-GNU: @f32([2 x i32] %s.coerce)
|
| aarch64-arguments.c | 129 // PCS: define void @f32(%struct.s32* %a)
131 void f32(struct s32 a) {} function
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 56 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
93 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
103 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
110 setOperationAction(ISD::SETCC, MVT::f32, Custom);
141 setOperationAction(ISD::FABS, MVT::f32, Legal);
144 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
147 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
150 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
153 setOperationAction(ISD::FNEG, MVT::f32, Legal)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 54 f32 = 8, // This is a 32 bit floating point value enumerator in enum:llvm::MVT::SimpleValueType
97 v2f32 = 42, // 2 x f32
98 v4f32 = 43, // 4 x f32
99 v8f32 = 44, // 8 x f32
100 v16f32 = 45, // 16 x f32
294 case v16f32: return f32;
367 case f32 :
449 return MVT::f32;
523 case MVT::f32:
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 122 case MVT::f32: return "f32";
188 case MVT::f32: return Type::getFloatTy(Context);
247 case Type::FloatTyID: return MVT(MVT::f32);
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 216 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
217 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
232 setOperationAction(ISD::SELECT, MVT::f32, Custom);
235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
237 setOperationAction(ISD::SETCC, MVT::f32, Custom);
241 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
245 setOperationAction(ISD::FABS, MVT::f32, Custom);
280 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
309 setOperationAction(ISD::FSIN, MVT::f32, Expand);
311 setOperationAction(ISD::FCOS, MVT::f32, Expand)
[all...] |
| /external/llvm/test/MC/ELF/ |
| cfi.s | 191 f32: label
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 87 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
94 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
142 setOperationAction(ISD::FSIN , MVT::f32, Expand);
143 setOperationAction(ISD::FCOS , MVT::f32, Expand);
144 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
145 setOperationAction(ISD::FREM , MVT::f32, Expand);
146 setOperationAction(ISD::FPOW , MVT::f32, Expand);
147 setOperationAction(ISD::FMA , MVT::f32, Legal);
154 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
158 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand)
[all...] |
