| /external/v8/src/arm/ |
| disasm-arm.cc | [all...] |
| /external/clang/test/CodeGen/ |
| x86_32-arguments-darwin.c | 135 // CHECK: define i32 @f32()
136 struct s32 { char a; unsigned : 0; } f32(void) { while (1) {} } function
|
| x86_64-arguments.c | 221 _Complex float f32(_Complex float A, _Complex float B) { function
223 // CHECK: define <2 x float> @f32(<2 x float> %A.coerce, <2 x float> %B.coerce)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 106 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
114 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
119 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
124 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
129 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
134 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
139 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
143 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
147 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
151 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32
[all...] |
| LegalizeDAG.cpp | 261 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
268 while (SVT != MVT::f32) {
656 if (CFP->getValueType(0) == MVT::f32 &&
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 52 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
|
| Mips16ISelDAGToDAG.cpp | 220 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
|
| /external/llvm/test/MC/ARM/ |
| neon-shuffle-encoding.s | 92 vtrn.f32 d3, d9
106 vtrn.f32 q14, q6
|
| neon-vld-encoding.s | 173 vld3.f32 {d1, d2, d3}, [r6]!
215 vld4.f32 {d16, d17, d18, d19}, [r3:64], r5
318 vld3.f32 {d1[1], d2[1], d3[1]}, [r6]!
355 vld3.f32 {d16[], d17[], d18[]}, [r3], r5
394 vld4.f32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5
431 vld4.f32 {d16[], d17[], d18[], d19[]}, [r3], r5
472 vld1.f32 {q2}, [r2]
|
| neon-add-encoding.s | 12 @ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf2]
13 vadd.f32 d16, d16, d17
14 @ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xf2]
15 vadd.f32 q8, q8, q9
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 54 /// When SSE is available, use it for f32 operations.
139 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
163 if (VT == MVT::f32 && !X86ScalarSSEf32)
205 case MVT::f32:
257 case MVT::f32:
871 case MVT::f32:
[all...] |
| X86ISelLowering.cpp | 248 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
251 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
282 // f32 and f64 cases are Legal, f80 case is not
293 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
305 // f32 and f64 cases are Legal, f80 case is not
342 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
379 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
392 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
393 setOperationAction(ISD::FREM , MVT::f32 , Expand);
459 setOperationAction(ISD::SELECT , MVT::f32 , Custom)
[all...] |
| X86ISelLowering.h | 690 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
732 /// When SSE is available, use it for f32 operations.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 436 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
440 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
454 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
617 // ARM does not have f32 extending load.
618 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
[all...] |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 99 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
104 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
155 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
157 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
172 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon.S | 308 vcvt.f32.s32 q3, q3
309 vcvt.f32.s32 q4, q4
312 vmla.f32 q10, q3, d0[0]
313 vmla.f32 q11, q4, d0[0]
354 vmul.f32 q0, q1, d6[0]
361 vmla.f32 q0, q1, d6[0]
362 vmla.f32 q0, q2, d6[1]
366 vcvt.s32.f32 q0, q0
398 vmla.f32 q0, q1, d4[0]
402 vcvt.s32.f32 q0, q
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 563 } else if (LHS.getValueType() == MVT::f32) {
[all...] |
| /external/skia/legacy/src/views/ |
| SkEvent.cpp | 16 f32 = 0;
|
| /external/skia/src/views/ |
| SkEvent.cpp | 16 f32 = 0;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 405 assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
451 assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64)
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 43 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
69 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
|
| /external/valgrind/main/memcheck/tests/ |
| deep-backtrace.c | 32 int f32(int *p) { return f31(p); } function
33 int f33(int *p) { return f32(p); }
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 64 case MVT::f32: return "MVT::f32";
|
| IntrinsicEmitter.cpp | 266 case MVT::f32: return Sig.push_back(IIT_F32);
|
