| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 152 const MCInstrDesc &MCID = MI->getDesc();
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| X86FloatingPoint.cpp | 416 uint64_t Flags = MI->getDesc().TSFlags;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 160 uint64_t TSFlags = MI.getDesc().TSFlags;
280 if (((MI->getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) &&
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| MipsLongBranch.cpp | 108 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
225 for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
382 assert(I.Br->getDesc().getNumOperands() == 1);
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| MipsInstrInfo.cpp | 277 return MI->getDesc().getSize();
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| MipsDelaySlotFiller.cpp | 298 update(MI, 0, MI.getDesc().getNumOperands());
308 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 564 const MCInstrDesc &MID = MI->getDesc();
586 const uint64_t F = MI->getDesc().TSFlags;
917 bool isPred = MI->getDesc().isPredicable();
[all...] |
| HexagonVLIWPacketizer.cpp | 351 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
[all...] |
| HexagonNewValueJump.cpp | 157 if (MII->getDesc().mayStore())
459 assert((MI->getDesc().isCompare()) &&
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| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 186 const MCInstrDesc &MCID = MI->getDesc();
343 const MCInstrDesc &MCID = MI->getDesc();
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| Thumb2ITBlockPass.cpp | 140 const MCInstrDesc &MCID = MI->getDesc();
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| Thumb2SizeReduction.cpp | 294 if (!HasImplicitCPSRDef(MI->getDesc()))
523 const MCInstrDesc &MCID = MI->getDesc();
673 const MCInstrDesc &MCID = MI->getDesc();
738 const MCInstrDesc &MCID = MI->getDesc();
[all...] |
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 386 if (i < MI->getDesc().getNumOperands())
387 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
460 if (i < MI->getDesc().getNumOperands())
461 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
[all...] |
| MachineInstr.cpp | 551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
757 if (MII->getDesc().getFlags() & Mask) {
[all...] |
| MachineLICM.cpp | 813 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
845 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
[all...] |
| MachineCSE.cpp | 514 unsigned NumDefs = MI->getDesc().getNumDefs() +
515 MI->getDesc().getNumImplicitDefs();
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| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.cpp | 230 return MI->getDesc().isPredicable();
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| /external/skia/legacy/src/ports/ |
| SkFontHost_FONTPATH.cpp | 311 SkDescriptor* desc = ad.getDesc();
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| /external/skia/src/ports/ |
| SkFontHost_FONTPATH.cpp | 312 SkDescriptor* desc = ad.getDesc();
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| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 255 /// getDesc - Returns the target instruction descriptor of this
257 const MCInstrDesc &getDesc() const { return *MCID; }
318 return getDesc().getFlags() & (1 << MCFlag);
[all...] |
| ScheduleDAG.h | 583 if (SU->isInstr()) return &SU->getInstr()->getDesc();
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| /external/skia/src/gpu/gl/ |
| GrGpuGL_program.cpp | 165 const ProgramDesc& desc = fCurrentProgram->getDesc();
213 const ProgramDesc& desc = fCurrentProgram->getDesc();
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| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 293 const MCInstrDesc &Desc = MI->getDesc();
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| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 163 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
177 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
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| /prebuilts/devtools/tools/lib/ |
| asm-4.0.jar | |
