| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 129 if (isIntS32Immediate(N.getOperand(1), imm))
132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
136 Base = N.getOperand(0);
137 Index = N.getOperand(1);
155 if (isIntS32Immediate(N.getOperand(1), imm)) {
157 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
160 Base = N.getOperand(0);
226 SDValue Chain = Node->getOperand(0);
227 SDValue Callee = Node->getOperand(1)
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 116 const MCOperand &MO = MI.getOperand(OpNo);
129 const MCOperand &MO2 = MI.getOperand(OpNo+1);
138 const MCOperand &MO = MI.getOperand(OpNo);
149 const MCOperand &MO = MI.getOperand(OpNo);
160 const MCOperand &MO = MI.getOperand(OpNo);
173 assert(MI.getOperand(OpNo+1).isReg());
174 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
176 const MCOperand &MO = MI.getOperand(OpNo);
195 assert(MI.getOperand(OpNo+1).isReg());
196 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreAsmPrinter.cpp | 202 unsigned JTI = MI->getOperand(opNum).getIndex();
218 const MachineOperand &MO = MI->getOperand(opNum);
276 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
280 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
291 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
293 return MachineLocation(MI->getOperand(0).getReg(),
294 MI->getOperand(1).getImm());
312 if (MI->getOperand(2).getImm() == 0)
[all...] |
| XCoreISelLowering.cpp | 221 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
222 Op.getOperand(3), Op.getOperand(4));
223 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
224 Op.getOperand(1));
332 SDValue Chain = Op.getOperand(0);
333 SDValue Table = Op.getOperand(1);
334 SDValue Index = Op.getOperand(2);
361 if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
365 const SDValue &Base = Addr.getOperand(0)
[all...] |
| /frameworks/compile/libbcc/bcinfo/ |
| MetadataExtractor.cpp | 158 llvm::MDNode *ObjectSlot = ObjectSlotMetadata->getOperand(i);
160 llvm::Value *SlotMDS = ObjectSlot->getOperand(0);
210 llvm::MDNode *Pragma = PragmaMetadata->getOperand(i);
212 llvm::Value *PragmaKeyMDS = Pragma->getOperand(0);
214 llvm::Value *PragmaValueMDS = Pragma->getOperand(1);
289 llvm::MDNode *Name = VarNameMetadata->getOperand(i);
291 TmpNameList[i] = createStringFromValue(Name->getOperand(0));
315 llvm::MDNode *Name = FuncNameMetadata->getOperand(i);
317 TmpNameList[i] = createStringFromValue(Name->getOperand(0));
362 llvm::MDNode *SigNode = Signatures->getOperand(i)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 45 (MI.getOperand(1).getReg() == Mips::ZERO) &&
46 (MI.getOperand(2).getImm() == 0)) {
47 DstReg = MI.getOperand(0).getReg();
50 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
51 (MI.getOperand(2).getImm() == 0)) {
52 DstReg = MI.getOperand(0).getReg();
62 MachineOperand &MO = U.getOperand();
185 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
186 N->getOperand(1));
210 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }
[all...] |
| MipsSERegisterInfo.cpp | 102 Offset += MI.getOperand(OpNo + 1).getImm();
123 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
124 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 45 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
46 MI->getOperand(2).getImm() == 0) {
47 FrameIndex = MI->getOperand(1).getIndex();
48 return MI->getOperand(0).getReg();
64 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
65 MI->getOperand(1).getImm() == 0) {
66 FrameIndex = MI->getOperand(0).getIndex();
67 return MI->getOperand(2).getReg()
[all...] |
| /external/llvm/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 67 const MachineOperand &MO = MI->getOperand(i);
124 const MachineOperand &MO = MI->getOperand(i);
134 MachineOperand& Use = I.getOperand();
139 UseMI->getOperand(0).setReg(0U);
153 const MachineOperand &MO = MI->getOperand(i);
172 const MachineOperand &MO = MI->getOperand(i);
|
| DwarfEHPrepare.cpp | 72 Value *V = RI->getOperand(0);
81 ExcIVI = dyn_cast<InsertValueInst>(SelIVI->getOperand(0));
82 if (ExcIVI && isa<UndefValue>(ExcIVI->getOperand(0)) &&
84 ExnObj = ExcIVI->getOperand(1);
85 SelLoad = dyn_cast<LoadInst>(SelIVI->getOperand(1));
92 ExnObj = ExtractValueInst::Create(RI->getOperand(0), 0, "exn.obj", RI);
|
| MachineSSAUpdater.cpp | 94 unsigned SrcReg = I->getOperand(i).getReg();
95 MachineBasicBlock *SrcBB = I->getOperand(i+1).getMBB();
102 return I->getOperand(0).getReg();
152 return NewDef->getOperand(0).getReg();
204 return InsertedPHI->getOperand(0).getReg();
211 if (&MI->getOperand(i) == U)
212 return MI->getOperand(i+1).getMBB();
272 unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
274 return PHI->getOperand(idx+1).getMBB();
300 return NewDef->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 107 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
115 Offset += MI.getOperand(FIOperandNum + 1).getImm();
120 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/ false);
121 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
151 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true);
152 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset / OffsetScale);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 133 assert(MII->getOperand(0).isMBB() &&
135 int Sub = InstOffset - BlockToInstOffset[MII->getOperand(0).getMBB()];
167 if (MII->getOperand(1).isReg()) {
170 .addReg(MII->getOperand(1).getReg());
174 .addImm(MII->getOperand(1).getImm());
180 .addMBB(MII->getOperand(0).getMBB());
|
| /external/llvm/lib/Transforms/Scalar/ |
| EarlyCSE.cpp | 96 Value *LHS = BinOp->getOperand(0);
97 Value *RHS = BinOp->getOperand(1);
98 if (BinOp->isCommutative() && BinOp->getOperand(0) > BinOp->getOperand(1))
113 Value *LHS = CI->getOperand(0);
114 Value *RHS = CI->getOperand(1);
116 if (Inst->getOperand(0) > Inst->getOperand(1)) {
124 return hash_combine(CI->getOpcode(), CI->getType(), CI->getOperand(0));
127 return hash_combine(EVI->getOpcode(), EVI->getOperand(0)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombinePHI.cpp | 28 Value *LHSVal = FirstInst->getOperand(0);
29 Value *RHSVal = FirstInst->getOperand(1);
49 I->getOperand(0)->getType() != LHSType ||
50 I->getOperand(1)->getType() != RHSType)
66 if (I->getOperand(0) != LHSVal) LHSVal = 0;
67 if (I->getOperand(1) != RHSVal) RHSVal = 0;
79 Value *InLHS = FirstInst->getOperand(0);
80 Value *InRHS = FirstInst->getOperand(1);
84 FirstInst->getOperand(0)->getName() + ".pn");
92 FirstInst->getOperand(1)->getName() + ".pn")
[all...] |
| InstCombineLoadStoreAlloca.cpp | 35 return pointsToConstantGlobal(CE->getOperand(0));
284 User *CI = cast<User>(LI.getOperand(0));
285 Value *CastOp = CI->getOperand(0);
338 Value *Op = LI.getOperand(0);
372 const Value *GEPI0 = GEPI->getOperand(0);
417 if (isSafeToLoadUnconditionally(SI->getOperand(1), SI, Align, TD) &&
418 isSafeToLoadUnconditionally(SI->getOperand(2), SI, Align, TD)) {
419 LoadInst *V1 = Builder->CreateLoad(SI->getOperand(1),
420 SI->getOperand(1)->getName()+".val");
421 LoadInst *V2 = Builder->CreateLoad(SI->getOperand(2)
[all...] |
| /external/llvm/lib/Target/XCore/InstPrinter/ |
| XCoreInstPrinter.cpp | 73 const MCOperand &Op = MI->getOperand(OpNo);
92 if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0)
|
| /frameworks/compile/libbcc/lib/Renderscript/ |
| RSInfoExtractor.cpp | 71 llvm::MDNode *node = pMetadata->getOperand(i);
77 llvm::StringRef s = getStringFromOperand(node->getOperand(j));
203 if (((_node) = (_metadata)->getOperand(i)) != NULL)
212 llvm::StringRef key = getStringFromOperand(node->getOperand(0));
213 llvm::StringRef val = getStringFromOperand(node->getOperand(1));
231 llvm::StringRef name = getStringFromOperand(node->getOperand(0));
248 llvm::StringRef name = getStringFromOperand(node->getOperand(0));
292 llvm::MDNode *name_node = export_foreach_name->getOperand(i);
293 llvm::MDNode *signature_node = export_foreach_signature->getOperand(i);
297 name = getStringFromOperand(name_node->getOperand(0))
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 63 dyn_cast<ConstantInt>(LocInfo->getOperand(ErrorLine)))
203 unsigned OpFlags = MI->getOperand(OpNo).getImm();
211 MI->getOperand(OpNo).isMetadata()) {
214 unsigned OpFlags = MI->getOperand(OpNo).getImm();
369 unsigned OpFlags = MI->getOperand(OpNo).getImm();
377 MI->getOperand(OpNo).isMetadata()) {
380 unsigned OpFlags = MI->getOperand(OpNo).getImm();
385 OS << *MI->getOperand(OpNo).getMBB()->getSymbol();
418 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef()
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 84 MachineOperand dest = MI.getOperand(0);
85 MachineOperand src = MI.getOperand(1);
195 TBB = LastInst->getOperand(0).getMBB();
199 TBB = LastInst->getOperand(1).getMBB();
200 Cond.push_back(LastInst->getOperand(0));
218 TBB = SecondLastInst->getOperand(1).getMBB();
219 Cond.push_back(SecondLastInst->getOperand(0));
220 FBB = LastInst->getOperand(0).getMBB();
228 TBB = SecondLastInst->getOperand(0).getMBB();
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 64 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
88 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
132 const MCOperand &Op = MI->getOperand(OpNo);
154 const MCOperand &Op = MI->getOperand(OpNo);
176 const MCOperand &BaseReg = MI->getOperand(Op);
177 const MCOperand &IndexReg = MI->getOperand(Op+2);
178 const MCOperand &DispSpec = MI->getOperand(Op+3);
179 const MCOperand &SegReg = MI->getOperand(Op+4);
206 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 61 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
69 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
71 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
114 User->getOperand(2).getNode() == Node &&
115 User->getOperand(2).getResNo() == ResNo) {
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
124 SDValue Op = User->getOperand(i);
197 User->getOperand(2).getNode() == Node &&
198 User->getOperand(2).getResNo() == ResNo)
[all...] |
| LegalizeTypesGeneric.cpp | 42 SDValue InOp = N->getOperand(0);
185 Lo = N->getOperand(0);
186 Hi = N->getOperand(1);
191 GetExpandedOp(N->getOperand(0), Lo, Hi);
192 SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ?
203 SDValue OldVec = N->getOperand(0);
219 OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0));
228 SDValue Idx = N->getOperand(1);
290 SDValue Chain = N->getOperand(0);
291 SDValue Ptr = N->getOperand(1)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 232 .addReg(MI.getOperand(1).getReg());
233 if (!MI.getOperand(1).isKill())
234 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
239 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
242 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
247 .addReg(MI.getOperand(1).getReg());
249 if (!MI.getOperand(1).isKill())
250 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
255 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
258 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill)
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 161 const MCOperand &MO = MI.getOperand(OpNo);
181 const MCOperand &MO = MI.getOperand(OpNo);
313 assert(MI.getOperand(OpNo).isReg());
314 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
315 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
323 assert(MI.getOperand(OpNo).isImm());
324 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
333 assert(MI.getOperand(OpNo-1).isImm());
334 assert(MI.getOperand(OpNo).isImm());
335 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups)
[all...] |
