/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 642 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 767 /// the search criteria to a use that kills the register if isKill is true. 768 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 773 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, 775 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeInstrInfo.h | 217 unsigned SrcReg, bool isKill, int FrameIndex,
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MBlazeInstrInfo.cpp | 94 unsigned SrcReg, bool isKill, int FI, 98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
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/external/llvm/lib/Target/R600/ |
AMDGPUInstrInfo.h | 81 unsigned SrcReg, bool isKill, int FrameIndex,
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AMDGPUInstrInfo.cpp | 126 unsigned SrcReg, bool isKill,
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/external/llvm/lib/CodeGen/ |
RegisterScavenging.cpp | 155 if (!isPred && MO.isKill()) 284 else if (MO.isKill())
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TargetInstrInfo.cpp | 141 bool Reg1IsKill = MI->getOperand(Idx1).isKill(); 142 bool Reg2IsKill = MI->getOperand(Idx2).isKill(); 399 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
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RegAllocFast.cpp | 638 } else if (MO.isKill()) { 645 } else if (MO.isKill()) { 671 return MO.isKill() || Dead; 680 if (MO.isKill()) { [all...] |
MachineVerifier.cpp | [all...] |
PostRASchedulerList.cpp | 438 if (!MO.isKill()) { 533 if (MO.isKill() != kill) {
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MachineLICM.cpp | 773 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg()); 827 bool isKill = isOperandKill(MO, MRI); 828 if (isNew && !isKill) 831 else if (!isNew && isKill) [all...] |
VirtRegMap.cpp | 297 if (MO.readsReg() && (MO.isDef() || MO.isKill()))
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/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 239 unsigned SrcReg, bool isKill, int FrameIndex, 243 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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/external/llvm/lib/Target/XCore/ |
XCoreInstrInfo.cpp | 363 unsigned SrcReg, bool isKill, 371 .addReg(SrcReg, getKillRegState(isKill))
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/external/llvm/lib/Target/ARM/ |
ARMExpandPseudoInsts.cpp | 461 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 548 getKillRegState(MO.isKill())); 592 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); [all...] |
Thumb2InstrInfo.cpp | 126 unsigned SrcReg, bool isKill, int FI, 143 .addReg(SrcReg, getKillRegState(isKill)) 148 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
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MLxExpansionPass.cpp | 279 bool Src1Kill = MI->getOperand(2).isKill(); 280 bool Src2Kill = MI->getOperand(3).isKill();
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ARMBaseInstrInfo.cpp | 249 if (MO.isUse() && MO.isKill()) { 764 unsigned SrcReg, bool isKill, int FI, 783 .addReg(SrcReg, getKillRegState(isKill)) 787 .addReg(SrcReg, getKillRegState(isKill)) 795 .addReg(SrcReg, getKillRegState(isKill)) 802 MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 813 .addReg(SrcReg, getKillRegState(isKill)) 817 .addReg(SrcReg, getKillRegState(isKill)) 830 .addReg(SrcReg, getKillRegState(isKill)) 837 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI) [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 233 if (!MI.getOperand(1).isKill()) 249 if (!MI.getOperand(1).isKill()) 295 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
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/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 210 false /*isKill*/, 308 Src.isKill(), Src.isDead(), Src.isUndef(),
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/external/llvm/lib/Target/Sparc/ |
DelaySlotFiller.cpp | 194 if (candidate->isImplicitDef() || candidate->isKill())
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/external/llvm/lib/Target/Mips/ |
Mips16InstrInfo.cpp | 102 unsigned SrcReg, bool isKill, int FI, 112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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MipsSEInstrInfo.cpp | 156 unsigned SrcReg, bool isKill, int FI, 177 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | 475 /// instruction. If isKill is true, the register operand is the last use and 479 unsigned SrcReg, bool isKill, int FrameIndex, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 335 bool isKill = Op.hasOneUse() && 339 if (isKill) { 347 isKill = false; 350 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | [all...] |