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  /dalvik/tests/002-sleep/
expected.txt 1 Sleeping 1000 msec...
  /external/valgrind/main/memcheck/tests/
nanoleak_supp.c 6 volatile int* a = malloc(1000);
  /prebuilts/gcc/darwin-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/
bversion.h 4 #define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)
  /prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/
bversion.h 4 #define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)
  /prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/
bversion.h 4 #define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)
  /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/
bversion.h 4 #define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)
  /device/asus/flo/
sec_config 3 16:4294967295:1000
thermald-flo.conf 11 sampling 1000
18 sampling 1000
25 sampling 1000
32 sampling 1000
39 sampling 1000
46 sampling 1000
53 sampling 1000
60 sampling 1000
67 sampling 1000
74 sampling 1000
    [all...]
  /external/clang/test/CodeGen/
2004-02-14-ZeroInitializer.c 4 int X[1000];
  /external/eigen/bench/btl/data/
go_mean 36 source mk_mean_script.sh matrix_vector $1 11 50 300 1000 $mode $prefix
37 source mk_mean_script.sh atv $1 11 50 300 1000 $mode $prefix
38 source mk_mean_script.sh matrix_matrix $1 11 100 300 1000 $mode $prefix
39 source mk_mean_script.sh aat $1 11 100 300 1000 $mode $prefix
40 # source mk_mean_script.sh ata $1 11 100 300 1000 $mode $prefix
41 source mk_mean_script.sh trmm $1 11 100 300 1000 $mode $prefix
42 source mk_mean_script.sh trisolve_vector $1 11 100 300 1000 $mode $prefix
43 source mk_mean_script.sh trisolve_matrix $1 11 100 300 1000 $mode $prefix
44 source mk_mean_script.sh cholesky $1 11 100 300 1000 $mode $prefix
45 source mk_mean_script.sh partial_lu_decomp $1 11 100 300 1000 $mode $prefi
    [all...]
  /external/llvm/test/CodeGen/Thumb/
thumb-imm.ll 5 ret i32 1000
  /external/valgrind/main/drd/tests/
hold_lock_1.vgtest 4 args: -i 1000
hold_lock_2.vgtest 4 args: -i 1000
  /external/valgrind/main/exp-bbv/tests/amd64-linux/
ll.stderr.exp 2 # Total intervals: 45 (Interval Size 1000)
  /external/valgrind/main/exp-bbv/tests/arm-linux/
ll.stderr.exp 2 # Total intervals: 47 (Interval Size 1000)
  /external/valgrind/main/exp-bbv/tests/ppc32-linux/
ll.stderr.exp 2 # Total intervals: 40 (Interval Size 1000)
  /external/valgrind/main/exp-bbv/tests/x86-linux/
ll.stderr.exp 2 # Total intervals: 39 (Interval Size 1000)
  /external/valgrind/main/massif/tests/
long-time.c 12 x1 = malloc( 800 * 1000);
13 x2 = malloc(1100 * 1000);
15 x3 = malloc(1200 * 1000);
18 x4 = malloc( 900 * 1000);
  /external/webkit/Source/WebCore/manual-tests/frames/resources/
blit-on-scroll-subsubframe.html 8 height: 1000px;
  /external/webkit/Source/WebCore/manual-tests/redirectHistory/
redir-3.html 5 window.setTimeout("window.history.back()", 1000);
  /external/oprofile/events/ppc64/power6/
events 28 event:0X0012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
32 event:0X0020 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP2 : (Group 2 pm_utilization_capacity) One of the threads in run cycles
34 event:0X0022 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP2 : (Group 2 pm_utilization_capacity) Concurrent run instructions
35 event:0X0023 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP2 : (Group 2 pm_utilization_capacity) Run PURR Event
38 event:0X0030 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP3 : (Group 3 pm_branch) A conditional branch was predicted, CR prediction
39 event:0X0031 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP3 : (Group 3 pm_branch) Branch mispredictions due to CR bit setting
40 event:0X0032 counters:2 um:zero minimum:1000 name:PM_BR_PRED_GRP3 : (Group 3 pm_branch) A conditional branch was predicted
41 event:0X0033 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_COUNT_GRP3 : (Group 3 pm_branch) Branch misprediction due to count prediction
44 event:0X0040 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP4 : (Group 4 pm_branch2) Branch count cache prediction
45 event:0X0041 counters:1 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP4 : (Group 4 pm_branch2) A conditional branch was predicted, link stac
    [all...]
  /external/oprofile/events/ppc64/power5++/
events 28 event:0X0012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
32 event:0X0020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
33 event:0X0021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empty
34 event:0X0022 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP2 : (Group 2 pm_completion) Group completed
38 event:0X0030 counters:0 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP3 : (Group 3 pm_group_dispatch) Group dispatch valid
39 event:0X0031 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP3 : (Group 3 pm_group_dispatch) Group dispatch rejected
40 event:0X0032 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP3 : (Group 3 pm_group_dispatch) Cycles group dispatch blocked by scoreboard
41 event:0X0033 counters:3 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_group_dispatch) Instructions dispatched
44 event:0X0040 counters:0 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles no instructions in CLB
45 event:0X0041 counters:1 um:zero minimum:1000 name:PM_2INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles 2 instructions in CL
    [all...]
  /external/llvm/test/CodeGen/X86/
lea-recursion.ll 11 @g0 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=8]
12 @g1 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=7]
16 %tmp4 = load i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 0) ; <i32> [#uses=1]
17 %tmp8 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 0) ; <i32> [#uses=1]
20 store i32 %tmp10, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 1)
21 %tmp8.1 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 1) ; <i32> [#uses=1]
24 store i32 %tmp10.1, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 2)
25 %tmp8.2 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 2) ; <i32> [#uses=1
    [all...]
  /external/oprofile/events/ppc64/ibm-compat-v1/
events 22 event:0X0010 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP1 : (Group 1 pm_compat_utilization1) At least one thread in run cycles
25 event:0X0013 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP1 : (Group 1 pm_compat_utilization1) Run PURR Even
28 event:0X0020 counters:0 um:zero minimum:1000 name:PM_FPU_FLOP_GRP2 : (Group 2 pm_compat_utilization2) FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
31 event:0X0023 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP2 : (Group 2 pm_compat_utilization2) Run instructions completed
34 event:0X0030 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L1-5_GRP3 : (Group 3 pm_compat_dsource) Data loaded from L1.5
35 event:0X0031 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP3 : (Group 3 pm_compat_dsource) Data loaded missed L2
36 event:0X0032 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP3 : (Group 3 pm_compat_dsource) Data loaded from private L3 miss
37 event:0X0033 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP3 : (Group 3 pm_compat_dsource) Run instructions completed
41 event:0X0041 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) Store instructions finished
42 event:0X0042 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) L1 D cache store misse
    [all...]
  /external/oprofile/events/ppc64/970MP/
events 25 event:0X0012 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP1 : (Group 1 pm_slice0) Completion stopped
27 event:0X0014 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP1 : (Group 1 pm_slice0) One or more PPC instruction completed
29 event:0X0016 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP1 : (Group 1 pm_slice0) Group completed
30 event:0X0017 counters:7 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP1 : (Group 1 pm_slice0) Group dispatch rejected
35 event:0X0022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
36 event:0X0023 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP2 : (Group 2 pm_eprof) L1 D cache entries invalidated from L2
37 event:0X0024 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP2 : (Group 2 pm_eprof) Instructions dispatched
39 event:0X0026 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache store references
40 event:0X0027 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load references
45 event:0X0032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misse
    [all...]

Completed in 1103 milliseconds

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