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  /dalvik/vm/mterp/x86/
OP_MUL_LONG.S 6 * this code. We spill rINSTw (ebx),
8 * temps. On top of that, we'll spill edi (rFP)
16 SPILL(rFP)
17 SPILL(rINST)
18 SPILL(rIBASE)
OP_MUL_LONG_2ADDR.S 6 * this code. We must spill %edx (rIBASE) because it
7 * is used by imul. We'll also spill rINST (ebx),
9 * temps. On top of that, we'll spill %esi (edi)
18 SPILL(rFP)
19 SPILL(rIBASE)
OP_CONST_WIDE_16.S 4 SPILL(rIBASE) # preserve rIBASE (cltd trashes it)
OP_CONST_WIDE_32.S 4 SPILL(rIBASE) # save rIBASE (cltd trashes it)
OP_MUL_INT.S 9 SPILL(rIBASE)
OP_MUL_INT_LIT8.S 6 SPILL(rIBASE)
OP_SHL_LONG_2ADDR.S 8 /* Need to spill rIBASE */
14 SPILL(rIBASE)
OP_SHR_LONG_2ADDR.S 8 /* Need to spill rIBASE */
14 SPILL(rIBASE)
OP_USHR_LONG_2ADDR.S 8 /* Need to spill rIBASE */
14 SPILL(rIBASE)
OP_BREAKPOINT.S 11 SPILL(rIBASE)
OP_FILL_ARRAY_DATA.S 9 SPILL(rIBASE)
OP_MONITOR_ENTER.S 15 SPILL(rIBASE)
OP_MUL_INT_2ADDR.S 7 SPILL(rIBASE)
OP_INT_TO_LONG.S 7 SPILL(rIBASE) # cltd trashes rIBASE/edx
OP_MUL_INT_LIT16.S 9 SPILL(rIBASE)
binopWide.S 8 SPILL(rIBASE) # save rIBASE
OP_CMP_LONG.S 9 // TUNING: rework to avoid rIBASE spill
12 SPILL(rIBASE)
OP_SHL_LONG.S 12 /* Need to spill rINST */
16 SPILL(rIBASE)
OP_SHR_LONG.S 12 /* Need to spill rIBASE */
16 SPILL(rIBASE)
OP_USHR_LONG.S 12 /* Need to spill rIBASE */
16 SPILL(rIBASE)
  /external/oprofile/module/ia64/
IA64minstate.h 192 st8.spill [r17]=rR1, 16; /* save original r1 */ \
194 .mem.offset 0, 0; st8.spill [r16]=r2, 16; \
195 .mem.offset 8, 0; st8.spill [r17]=r3, 16; \
198 .mem.offset 0, 0; st8.spill [r16]=r12, 16; \
199 .mem.offset 8, 0; st8.spill [r17]=r13, 16; \
203 .mem.offset 0, 0; st8.spill [r16]=r14, 16; \
204 .mem.offset 8, 0; st8.spill [r17]=r15, 16; \
207 .mem.offset 0, 0; st8.spill [r16]=r8, 16; \
208 .mem.offset 8, 0; st8.spill [r17]=r9, 16; \
212 .mem.offset 0, 0; st8.spill [r16]=r10, 16;
    [all...]
  /external/llvm/lib/CodeGen/
Spiller.h 22 /// Implementations are utility classes which insert spill or remat code on
29 /// spill - Spill the LRE.getParent() live interval.
30 virtual void spill(LiveRangeEdit &LRE) = 0;
39 /// Create and return a spiller that will insert spill code directly instead
RegAllocBasic.cpp 56 /// algorithm. It prioritizes live virtual registers by spill weight and spills
164 // Spill or split all live virtual registers currently unified under PhysReg
190 // Spill each interfering vreg allocated to PhysReg or an alias.
192 LiveInterval &Spill = *Intfs[i];
195 if (!VRM->hasPhys(Spill.reg))
200 Matrix->unassign(Spill);
202 // Spill the extracted interval.
203 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM);
204 spiller().spill(LRE);
223 // Populate a list of physical register spill candidates
    [all...]
SpillPlacement.h 1 //===-- SpillPlacement.h - Optimal Spill Code Placement --------*- C++ -*--===//
10 // This analysis computes the optimal spill code placement between basic blocks.
21 // The returned bit vector can be used to place optimal spill code at basic
22 // block entries and exits. Spill code placement inside a basic block is not
86 /// the stack can be live-out on the stack without inserting a spill.
90 /// prepare - Reset state and prepare for a new spill placement computation.
109 /// @param Blocks Array of block numbers that prefer to spill in and out.
131 /// finish - Compute the optimal spill code placement given the
  /external/llvm/include/llvm/CodeGen/
CalcSpillWeights.h 23 /// normalizeSpillWeight - The spill weight of a live interval is computed as:
34 // intervals have a spill weight that is mostly proportional to the number
35 // of uses, while large intervals get a spill weight that is closer to a use
41 /// register such as its spill weight and allocation hint.
52 /// CalculateWeightAndHint - (re)compute li's spill weight and allocation
57 /// CalculateSpillWeights - Compute spill weights for all virtual register

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