| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 178 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
269 && I->getOpcode() != SP::BCOND
|
| SparcInstrInfo.td | 520 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
[all...] |
| SparcISelLowering.cpp | [all...] |
| /external/qemu/target-mips/ |
| machine.c | 86 i = env->bcond;
238 env->bcond = i;
|
| translate.c | 432 static TCGv cpu_dspctrl, btarget, bcond; variable
[all...] |
| cpu.h | 448 target_ulong bcond; /* Branch condition (if needed) */ member in struct:CPUMIPSState
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.td | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| mips_disassem.c | 69 /* 0 */ "spec", "bcond","j ", "jal", "beq", "bne", "blez", "bgtz",
|
