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  /external/valgrind/main/none/tests/mips32/
round.c 126 __asm__ volatile("cfc1 $t0, $31\n\t"
133 __asm__ volatile("cfc1 $t0, $31\n\t"
140 __asm__ volatile("cfc1 $t0, $31\n\t"
147 __asm__ volatile("cfc1 $t0, $31\n\t"
  /development/ndk/sources/android/libportable/arch-mips/
fenv.c 112 __asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr));
_setjmp.S 93 cfc1 v0, $31
setjmp.S 107 cfc1 v0, $31
  /bionic/libm/include/mips/
fenv.h 107 __asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr));
  /development/ndk/platforms/android-9/arch-mips/include/
fenv.h 107 __asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr));
  /external/qemu/target-mips/
helper.h 167 DEF_HELPER_1(cfc1, tl, i32)
  /bionic/libc/arch-mips/bionic/
_setjmp.S 87 cfc1 v0, $31
setjmp.S 100 cfc1 v0, $31
  /external/v8/test/cctest/
test-assembler-mips.cc 1174 __ cfc1(a1, FCSR);
1197 __ cfc1(a2, FCSR);
    [all...]
  /external/llvm/test/MC/Mips/
mips-fpu-instructions.s 142 # CHECK: cfc1 $6, $fcc0 # encoding: [0x00,0x00,0x46,0x44]
161 cfc1 $a2,$0
  /external/llvm/test/MC/Disassembler/Mips/
mips32.txt 162 # CHECK: cfc1 $6, $7
mips32_le.txt 162 # CHECK: cfc1 $6, $7
mips32r2.txt 162 # CHECK: cfc1 $6, $7
mips32r2_le.txt 162 # CHECK: cfc1 $6, $7
  /external/llvm/lib/Target/Mips/
MipsInstrFPU.td 278 def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
MipsSEInstrInfo.cpp 95 Opc = Mips::CFC1;
  /external/v8/src/mips/
disasm-mips.cc 482 case CFC1:
483 Format(instr, "cfc1 'rt, 'fs");
macro-assembler-mips.cc     [all...]
constants-mips.h 361 CFC1 = ((0 << 3) + 2) << 21,
assembler-mips.cc 1667 void Assembler::cfc1(Register rt, FPUControlRegister fs) { function in class:v8::Assembler
    [all...]
  /system/core/libpixelflinger/codeflinger/
mips_disassem.c 445 db_printf("cfc1\t%s,f%d",
  /bionic/libc/kernel/arch-mips/asm/
mipsregs.h     [all...]
  /development/ndk/platforms/android-9/arch-mips/include/asm/
mipsregs.h     [all...]
  /external/kernel-headers/original/asm-mips/
mipsregs.h 1010 "cfc1\t%0,"STR(source)"\n\t" \
    [all...]

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