| /external/valgrind/main/none/tests/mips32/ |
| round.c | 129 "ctc1 $t0, $31\n\t");
137 "ctc1 $t0, $31\n\t");
144 "ctc1 $t0, $31\n\t");
151 "ctc1 $t0, $31\n\t");
|
| /development/ndk/sources/android/libportable/arch-mips/ |
| fenv.c | 121 __asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr));
|
| _setjmp.S | 150 ctc1 v0, $31
|
| setjmp.S | 182 ctc1 v0, $31
|
| /bionic/libm/include/mips/ |
| fenv.h | 116 __asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr));
|
| /development/ndk/platforms/android-9/arch-mips/include/ |
| fenv.h | 116 __asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr));
|
| /external/qemu/target-mips/ |
| helper.h | 168 DEF_HELPER_2(ctc1, void, tl, i32)
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 1176 __ ctc1(zero_reg, FCSR);
1195 __ ctc1(zero_reg, FCSR); \
[all...] |
| /bionic/libc/arch-mips/bionic/ |
| _setjmp.S | 144 ctc1 v0, $31
|
| setjmp.S | 175 ctc1 v0, $31
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 171 # CHECK: ctc1 $6, $7
|
| mips32_le.txt | 171 # CHECK: ctc1 $6, $7
|
| mips32r2.txt | 171 # CHECK: ctc1 $6, $7
|
| mips32r2_le.txt | 171 # CHECK: ctc1 $6, $7
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 279 def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
|
| MipsSEInstrInfo.cpp | 105 Opc = Mips::CTC1;
|
| /external/v8/src/mips/ |
| disasm-mips.cc | 479 case CTC1:
480 Format(instr, "ctc1 'rt, 'fs");
|
| constants-mips.h | 364 CTC1 = ((0 << 3) + 6) << 21,
|
| assembler-mips.cc | 1662 void Assembler::ctc1(Register rt, FPUControlRegister fs) { function in class:v8::Assembler
[all...] |
| assembler-mips.h | 803 void ctc1(Register rt, FPUControlRegister fs);
[all...] |
| macro-assembler-mips.cc | [all...] |
| simulator-mips.cc | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| mips_disassem.c | 439 db_printf("ctc1\t%s,f%d",
|
| /external/valgrind/main/VEX/priv/ |
| host_mips_defs.c | [all...] |
| guest_mips_toIR.c | [all...] |
