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  /external/valgrind/main/cachegrind/tests/
chdir.stderr.exp 4 I1 misses:
5 LLi misses:
10 D1 misses:
11 LLd misses:
16 LL misses:
dlclose.stderr.exp 4 I1 misses:
5 LLi misses:
10 D1 misses:
11 LLd misses:
16 LL misses:
notpower2.stderr.exp 4 I1 misses:
5 LLi misses:
10 D1 misses:
11 LLd misses:
16 LL misses:
wrap5.stderr.exp 4 I1 misses:
5 LLi misses:
10 D1 misses:
11 LLd misses:
16 LL misses:
filter_stderr 13 # Remove numbers from I1/D1/LL/LLi/LLd "misses:" and "miss rates:" lines
14 perl -p -e 's/((I1|D1|LL|LLi|LLd) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' |
  /external/valgrind/main/cachegrind/tests/x86/
fpu-28-108.stderr.exp 4 I1 misses:
5 LLi misses:
10 D1 misses:
11 LLd misses:
16 LL misses:
  /external/valgrind/main/callgrind/tests/
notpower2-hwpref.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
notpower2-use.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
notpower2-wb.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
notpower2.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
simwork-cache.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
simwork1.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
simwork2.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
simwork3.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
threads-use.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
simwork-both.stderr.exp 7 I1 misses:
8 LLi misses:
13 D1 misses:
14 LLd misses:
19 LL misses:
  /external/webkit/LayoutTests/http/tests/appcache/
top-frame-1-expected.txt 3 Techically, the check is that iframe subresources that are not in top frame cache are loaded anyway, so it can also pass if the UA fails to reject loads for cache misses.
  /external/oprofile/events/mips/vr5432/
events 12 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
13 event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
  /external/oprofile/events/alpha/ev6/
events 7 event:0x04 counters:1 um:zero minimum:500 name:DTB_MISS : Retired DTB single misses * 2
8 event:0x05 counters:1 um:zero minimum:500 name:DTB_DD_MISS : Retired DTB double double misses
9 event:0x06 counters:1 um:zero minimum:500 name:ITB_MISS : Retired ITB misses
  /external/oprofile/events/ppc64/pa6t/
events 16 event:0x12 counters:2 um:zero minimum:1000 name:GRP1_DCACHE_RD_MISS__NS : Dcache read misses NS
17 event:0x13 counters:3 um:zero minimum:500 name:GRP1_MRB_LD_MISS_L2__NS : Load misses filling from memory
18 event:0x14 counters:4 um:zero minimum:500 name:GRP1_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and allocates an MRB entry
19 event:0x15 counters:5 um:zero minimum:500 name:GRP1_TLB_MISS_D__NS : TLB misses NS (D- only)
40 event:0x42 counters:2 um:zero minimum:500 name:GRP4_TLB_MISS_D__NS : TLB Misses (D-)
41 event:0x43 counters:3 um:zero minimum:500 name:GRP4_TLB_MISS_I__NS : TLB MIsses (I-)
42 event:0x44 counters:4 um:zero minimum:500 name:GRP4_DERAT_MISS__NS : DERAT Misses
43 event:0x45 counters:5 um:zero minimum:500 name:GRP4_IERAT_MISS__NS : IERAT Misses
48 event:0x52 counters:2 um:zero minimum:500 name:GRP5_DCACHE_RD_MISS__NS : Dcache read misses NS
49 event:0x53 counters:3 um:zero minimum:500 name:GRP5_MRB_LD_MISS_L2__NS : Load misses filling from memor
    [all...]
  /external/oprofile/events/mips/rm9000/
events 13 event:0x0a counters:0,1 um:zero minimum:500 name:L2_CACHE_MISSES : L2 cache misses
14 event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Icache misses
15 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Dcache misses
16 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
17 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
18 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
19 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
  /external/oprofile/events/i386/athlon/
events 7 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
9 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
17 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISSES_L2_DTLD_HITS : L1 DTLB misses and L2 DTLB hits
18 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_DTLB_MISSES : L1 and L2 DTLB misses
20 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISSES_L2_ITLB_HITS : L1 ITLB misses (and L2 ITLB hits)
21 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_ITLB_MISSES : L1 and L2 ITLB misses
  /external/oprofile/events/arm/armv6/
events.h 3 "number of instruction fetch misses"},
9 "number of Instruction MicroTLB misses"},
11 "number of Data MicroTLB misses"},
  /external/oprofile/events/mips/rm7000/
events 12 event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
14 event:0x0a counters:0,1 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses
15 event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
16 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
17 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
18 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
19 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
20 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
26 event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_MISSES : Cache misses
  /external/oprofile/events/mips/loongson2/
events 7 event:0x04 counters:0 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
23 event:0x14 counters:1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
31 event:0x1c counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
33 event:0x1e counters:1 um:zero minimum:500 name:LOAD_SPECULATION_MISSES : Load speculation misses

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