/external/llvm/test/CodeGen/Mips/ |
buildpairextractelementf64.ll | 7 ; CHECK: mtc1 8 ; CHECK: mtc1
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2008-08-04-Bitconvert.ll | 5 ; CHECK: mtc1
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constantfp0.ll | 5 ; CHECK: mtc1 $zero, $f[[R0:[0-9]+]]
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fabs.ll | 13 ; 32: mtc1 $[[AND]], $f0 16 ; 32R2: mtc1 $[[INS]], $f0 32 ; 32: mtc1 $[[AND]], $f1 35 ; 32R2: mtc1 $[[INS]], $f1
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fcopysign.ll | 15 ; 32: mtc1 $[[OR]], $f1 19 ; 32R2: mtc1 $[[INS]], $f1 48 ; 32: mtc1 $[[OR]], $f0 52 ; 32R2: mtc1 $[[INS]], $f0
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fcopysign-f32-f64.ll | 17 ; 64: mtc1 $[[OR]], $f0 21 ; 64R2: mtc1 $[[INS]], $f0
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/external/valgrind/main/none/tests/mips32/ |
MoveIns.c | 62 // mtc1 rt, fs 145 "mtc1 $t0, $f0\n\t" \ 146 "mtc1 $t1, $f2\n\t" \ 167 "mtc1 $t0, $f0\n\t" \ 168 "mtc1 $t1, $f2\n\t" \ 191 "mtc1 $t0, $f0\n\t" \ 192 "mtc1 $t1, $f2\n\t" \ 217 "mtc1 $0, $" #FD "\n\t" \ 238 "mtc1 $0, $" #FD "\n\t" \ 239 "mtc1 $0, $" #FD + 1"\n\t" [all...] |
MoveIns.stdout.exp | 29 MTC1 30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266 31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666 32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000 33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0 34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000 35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0 36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b 37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a 38 mtc1 $v1, $f8 :: fs nan, rt 0xfffffff [all...] |
MoveIns.stdout.exp-BE | 29 MTC1 30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266 31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666 32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000 33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0 34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000 35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0 36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b 37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a 38 mtc1 $v1, $f8 :: fs nan, rt 0xfffffff [all...] |
round.c | 109 "mtc1 %1, $f0\n\t" \ 117 "mtc1 %1, $f0\n\t" \
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/external/llvm/lib/Target/Mips/ |
MipsInstrFPU.td | 281 def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>; 452 // This pseudo instr gets expanded into 2 mtc1 instrs after register 470 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 471 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 473 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; 478 (CVT_D32_W (MTC1 CPURegs:$src))>; 490 (CVT_D64_W (MTC1 CPURegs:$src))>;
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MipsSEInstrInfo.cpp | 107 Opc = Mips::MTC1; 351 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 355 // mtc1 Lo, $fp 356 // mtc1 Hi, $fp + 1
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/external/v8/test/cctest/ |
test-assembler-mips.cc | 303 __ mtc1(t0, f14); 372 __ mtc1(t0, f6); 373 __ mtc1(t1, f7); 374 __ mtc1(t2, f4); 375 __ mtc1(t3, f5); 441 __ mtc1(t0, f12); 446 __ mtc1(t1, f14); 804 __ mtc1(t0, f8); // f8 has LS 32-bits. 805 __ mtc1(t1, f9); // f9 has MS 32-bits. [all...] |
/external/webkit/Source/JavaScriptCore/assembler/ |
MacroAssemblerMIPS.h | [all...] |
/development/ndk/sources/android/libportable/arch-mips/ |
_setjmp.S | 56 mtc1 t1, FPR ; \
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setjmp.S | 56 mtc1 t1, FPR ; \
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/bionic/libc/arch-mips/bionic/ |
_setjmp.S | 55 mtc1 t1, FPR ; \
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setjmp.S | 56 mtc1 t1, FPR ; \
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/external/v8/src/mips/ |
macro-assembler-mips.cc | 999 mtc1(at, fd); 1012 mtc1(at, FPURegister::from_code(scratch.code() + 1)); 1013 mtc1(zero_reg, scratch); 1025 mtc1(t8, fd); 1032 mtc1(t8, FPURegister::from_code(fs.code() + 1)); 1042 mtc1(t8, FPURegister::from_code(fs.code() + 1)); 1053 mtc1(t8, FPURegister::from_code(fs.code() + 1)); 1064 mtc1(t8, FPURegister::from_code(fs.code() + 1)); 1079 mtc1(at, FPURegister::from_code(scratch.code() + 1)); 1080 mtc1(zero_reg, scratch) [all...] |
/dalvik/vm/compiler/codegen/mips/Mips32/ |
Factory.cpp | 63 /* note the operands are swapped for the mtc1 instr */ 875 /* note the operands are swapped for the mtc1 instr */
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/external/llvm/test/MC/Mips/ |
mips-fpu-instructions.s | 148 # CHECK: mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44] 167 mtc1 $a2,$f7
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/external/llvm/test/MC/Disassembler/Mips/ |
mips32.txt | 270 # CHECK: mtc1 $6, $f7
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mips32_le.txt | 270 # CHECK: mtc1 $6, $f7
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mips32r2.txt | 279 # CHECK: mtc1 $6, $f7
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mips32r2_le.txt | 279 # CHECK: mtc1 $6, $f7
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