| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Ralloc.cpp | 33 bool fpHint, int regClass)
43 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
55 int regClass)
60 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
|
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Ralloc.cpp | 30 int regClass)
37 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
51 int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
54 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
|
| /external/llvm/test/TableGen/ |
| MultiPat.td | 72 def REGCLASS : RegisterClass<[], []>;
97 !subst(REGCLASS, VR128,
102 !subst(REGCLASS, VR128,
115 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],
116 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
117 (MNEMONIC REGCLASS:$dst, REGCLASS:$src)]]>
[all...] |
| TargetInstrSpec.td | 64 def REGCLASS : RegisterClass<[], []>;
85 !subst(REGCLASS, VR128, Decls.operand))))>;
92 !subst(REGCLASS, VR128, Decls.operand))))>;
96 [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 417 /// \brief Test if RegClass is one of the VSrc classes
418 static bool isVSrc(unsigned RegClass) {
419 return AMDGPU::VSrc_32RegClassID == RegClass ||
420 AMDGPU::VSrc_64RegClassID == RegClass;
423 /// \brief Test if RegClass is one of the SSrc classes
424 static bool isSSrc(unsigned RegClass) {
425 return AMDGPU::SSrc_32RegClassID == RegClass ||
426 AMDGPU::SSrc_64RegClassID == RegClass;
493 /// \brief Does "Op" fit into register class "RegClass" ?
495 unsigned RegClass) const
[all...] |
| SIISelLowering.h | 35 bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const;
37 unsigned RegClass, bool &ScalarSlotUsed) const;
|
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Ralloc.cpp | 30 int regClass)
41 int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXIntrinsics.td | 85 multiclass SAT<NVPTXRegClass regclass, Operand fimm, Intrinsic IntMinOp,
89 def SAT11 : NVPTXInst<(outs regclass:$dst),
90 (ins fimm:$srcf0, fimm:$srcf1, regclass:$src),
92 [(set regclass:$dst, (IntMinOp f1:$srcf0 ,
93 (IntMaxOp f0:$srcf1, regclass:$src)))]>;
96 def SAT12 : NVPTXInst<(outs regclass:$dst),
97 (ins fimm:$srcf0, fimm:$srcf1, regclass:$src),
99 [(set regclass:$dst, (IntMinOp f1:$srcf0 ,
100 (IntMaxOp regclass:$src, f0:$srcf1)))]>;
103 def SAT13 : NVPTXInst<(outs regclass:$dst)
[all...] |
| NVPTXVector.td | 241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
243 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a, regclass:$b),
245 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
257 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a)
[all...] |
| NVPTXInstrInfo.td | [all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Codegen.h | 65 bool fpHint, int regClass);
68 int regClass);
|
| RallocUtil.cpp | 318 int regClass)
321 switch(regClass) {
678 static bool regClassMatches(int regClass, int reg)
680 if (regClass == kAnyReg) {
682 } else if (regClass == kCoreReg) {
819 int regClass, bool update)
832 if (!regClassMatches(regClass, loc.lowReg)) {
834 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
855 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
870 int regClass, bool update
[all...] |
| /development/ndk/sources/android/libportable/arch-arm/ |
| unwind.c | 44 _Unwind_VRS_RegClass regclass,
50 _Unwind_VRS_RegClass regclass,
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
80 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
81 (AMDGPU::SSrc_64RegClassID == RegClass) ||
82 (AMDGPU::VSrc_32RegClassID == RegClass) ||
83 (AMDGPU::VSrc_64RegClassID == RegClass);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrArithmetic.td | 585 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
597 /// RegClass - This is the register class associated with this type. For
599 RegisterClass RegClass = regclass;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 108 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
119 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
121 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
122 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /ndk/sources/cxx-stl/gabi++/include/ |
| unwind-arm.h | 123 _Unwind_VRS_RegClass regclass,
129 _Unwind_VRS_RegClass regclass,
|
| /dalvik/vm/compiler/codegen/ |
| Ralloc.h | 80 int regClass, bool update);
211 bool fpHint, int regClass);
214 int regClass);
|
| RallocUtil.cpp | 317 int regClass)
320 switch(regClass) {
606 static bool regClassMatches(int regClass, int reg)
608 if (regClass == kAnyReg) {
610 } else if (regClass == kCoreReg) {
747 int regClass, bool update)
760 if (!regClassMatches(regClass, loc.lowReg)) {
762 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
783 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
798 int regClass, bool update
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
76 RCInfo &RCI = RegClass[RC->getID()];
112 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
|
| MachineRegisterInfo.cpp | 93 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
94 assert(RegClass && "Cannot create register without RegClass!");
95 assert(RegClass->isAllocatable() &&
96 "Virtual register RegClass must be allocatable.");
101 VRegInfo[Reg].first = RegClass;
|
| /prebuilts/ndk/4/platforms/android-3/arch-arm/usr/lib/ |
| libdl.so | |
| /prebuilts/ndk/4/platforms/android-4/arch-arm/usr/lib/ |
| libdl.so | |
| /prebuilts/ndk/4/platforms/android-5/arch-arm/usr/lib/ |
| libdl.so | |
| /prebuilts/ndk/4/platforms/android-8/arch-arm/usr/lib/ |
| libdl.so | |
