| /external/llvm/test/TableGen/ |
| Tree.td | 6 class RegisterClass;
11 def R32 : RegisterClass;
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| TreeNames.td | 6 class RegisterClass;
11 def R32 : RegisterClass;
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| TargetInstrSpec.td | 36 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
58 def VR128 : RegisterClass<[v2i64, v2f64],
64 def REGCLASS : RegisterClass<[], []>;
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| MultiPat.td | 44 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
66 def VR128 : RegisterClass<[v2i64, v2f64],
72 def REGCLASS : RegisterClass<[], []>;
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| Slice.td | 34 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
56 def FR32 : RegisterClass<[f32],
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| cast.td | 35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
57 def VR128 : RegisterClass<[v2i64, v2f64],
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| TargetInstrInfo.td | 11 class RegisterClass;
35 def R8 : RegisterClass;
36 def R16 : RegisterClass;
37 def R32 : RegisterClass;
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| /external/jmonkeyengine/engine/src/networking/com/jme3/network/serializing/ |
| Serializer.java | 100 registerClass(boolean.class, new BooleanSerializer());
101 registerClass(byte.class, new ByteSerializer());
102 registerClass(char.class, new CharSerializer());
103 registerClass(short.class, new ShortSerializer());
104 registerClass(int.class, new IntSerializer());
105 registerClass(long.class, new LongSerializer());
106 registerClass(float.class, new FloatSerializer());
107 registerClass(double.class, new DoubleSerializer());
109 registerClass(Boolean.class, new BooleanSerializer());
110 registerClass(Byte.class, new ByteSerializer())
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600RegisterInfo.td | 68 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
79 def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
86 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
89 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
92 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
95 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
99 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
107 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
110 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (ad
[all...] |
| AMDGPUInstructions.td | 114 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
121 class FABS <RegisterClass rc> : AMDGPUShaderInst <
128 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
137 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
165 RegisterClass rc> : Pat <
175 RegisterClass vec_class, int sub_idx,
183 RegisterClass elem_class, RegisterClass vec_class,
192 class Vector1_Build <ValueType vecType, RegisterClass vectorClass,
193 ValueType elemType, RegisterClass elemClass> : Pat
[all...] |
| SIRegisterInfo.td | 42 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
89 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
140 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
141 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
142 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
143 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
146 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
150 def SReg_64 : RegisterClass<"AMDGPU", [i64, i1], 64,
154 def SReg_128 : RegisterClass<"AMDGPU", [v16i8], 128, (add SGPR_128)>;
156 def SReg_256 : RegisterClass<"AMDGPU", [v32i8], 256, (add SGPR_256)>
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 67 def GPR32 : RegisterClass<"AArch64", [i32], 32,
71 def GPR64 : RegisterClass<"AArch64", [i64], 64,
75 def GPR32nowzr : RegisterClass<"AArch64", [i32], 32,
79 def GPR64noxzr : RegisterClass<"AArch64", [i64], 64,
86 def tcGPR64 : RegisterClass<"AArch64", [i64], 64,
94 def GPR32wsp : RegisterClass<"AArch64", [i32], 32,
98 def GPR64xsp : RegisterClass<"AArch64", [i64], 64,
105 def Rxsp : RegisterClass<"AArch64", [i64], 64,
109 def Rwsp : RegisterClass<"AArch64", [i32], 32,
140 def FPR8 : RegisterClass<"AArch64", [i8], 8
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.td | 292 def GR8 : RegisterClass<"X86", [i8], 8,
301 def GR16 : RegisterClass<"X86", [i16], 16,
305 def GR32 : RegisterClass<"X86", [i32], 32,
312 def GR64 : RegisterClass<"X86", [i64], 64,
319 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
322 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
325 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
333 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
334 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
335 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsCondMov.td | 19 class CMov_I_I_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
27 class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
35 class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
45 class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
80 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC
[all...] |
| MipsRegisterInfo.td | 261 RegisterClass<"Mips", regTypes, 32, (add
278 def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
292 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
298 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
300 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
309 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
311 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
323 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
326 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
329 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>, Unallocatable
[all...] |
| MipsInstrFPU.td | 89 class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
107 class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
132 class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
137 class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
142 class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC,
147 class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
152 class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin
[all...] |
| MipsInstrInfo.td | 413 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
429 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
437 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
444 multiclass LoadM<string opstr, RegisterClass RC,
453 multiclass StoreM<string opstr, RegisterClass RC,
464 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
473 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
480 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
490 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
501 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC>
[all...] |
| MipsDSPInstrInfo.td | 251 InstrItinClass itin, RegisterClass RCD,
252 RegisterClass RCS, RegisterClass RCT = RCS> {
262 InstrItinClass itin, RegisterClass RCD,
263 RegisterClass RCS = RCD> {
273 InstrItinClass itin, RegisterClass RCS,
274 RegisterClass RCT = RCS> {
284 InstrItinClass itin, RegisterClass RCD,
285 RegisterClass RCS, RegisterClass RCT = RCS>
[all...] |
| /external/clang/test/SemaObjC/ |
| super-dealloc-attribute.m | 23 + (void)registerClass:(id)name __attribute((objc_requires_super));
47 + (void)registerClass:(id)name {} // expected-warning {{method possibly missing a [super registerClass:] call}}
83 + (void)registerClass:(id)name {
84 [super registerClass:name]; // no-warning
|
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 187 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
203 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
215 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>;
221 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
230 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
233 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
239 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
247 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
256 def SPR : RegisterClass<"ARM", [f32], 32, (add (decimate
262 def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)>
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 165 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
169 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
180 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
182 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
184 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
189 def CRBITRC : RegisterClass<"PPC", [i32], 32,
202 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
208 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
211 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
215 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>
[all...] |
| /external/jmonkeyengine/engine/src/test/jme3test/network/ |
| TestMessages.java | 68 Serializer.registerClass(PingMessage.class);
69 Serializer.registerClass(PongMessage.class);
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| TestSerialization.java | 143 Serializer.registerClass(SomeObject.class);
144 Serializer.registerClass(TestSerializationMessage.class);
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| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.td | 45 def GRRegs : RegisterClass<"XCore", [i32], 32,
54 def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> {
|
| /external/chromium/base/win/ |
| wrapped_window_proc_unittest.cc | 64 RegisterClass(&wc);
|
