| /external/llvm/lib/Target/X86/ |
| X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
16 // SetCC instructions.
80 // SetCC instructions.
81 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
94 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
95 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
96 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
97 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
98 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
99 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal t
[all...] |
| X86TargetTransformInfo.cpp | 287 { ISD::SETCC, MVT::v2f64, 1 },
288 { ISD::SETCC, MVT::v4f32, 1 },
289 { ISD::SETCC, MVT::v2i64, 1 },
290 { ISD::SETCC, MVT::v4i32, 1 },
291 { ISD::SETCC, MVT::v8i16, 1 },
292 { ISD::SETCC, MVT::v16i8, 1 },
296 { ISD::SETCC, MVT::v4f64, 1 },
297 { ISD::SETCC, MVT::v8f32, 1 },
299 { ISD::SETCC, MVT::v4i64, 4 },
300 { ISD::SETCC, MVT::v8i32, 4 }
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 111 COMPARE(and_(r2, r3, Operand(r4), SetCC),
118 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
122 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
131 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
138 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
147 COMPARE(add(r7, r8, Operand(ip), SetCC),
149 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
156 COMPARE(adc(r5, sp, Operand(ip), SetCC),
158 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| setcc-takes-i32.ll | 4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
|
| /external/llvm/test/CodeGen/Mips/ |
| sitofp-selectcc-opt.ll | 8 ; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
|
| /external/llvm/test/CodeGen/R600/ |
| legalizedag-bug-expand-setcc.ll | 5 ; setcc to select_cc.
|
| fcmp.ll | 17 ; This test checks that a setcc node with f32 operands is lowered to a
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| exit_compare_live_range.ll | 2 ; having overlapping live ranges that result in copies. We want the setcc
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrFPU.td | 140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
153 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
157 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
163 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
166 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
169 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT)
[all...] |
| MBlazeInstrInfo.td | 763 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETEQ),
765 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETNE),
767 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGT),
769 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLT),
771 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGE),
773 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLE),
775 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGT),
778 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULT),
781 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGE),
784 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULE)
[all...] |
| MBlazeISelLowering.h | 104 /// getSetCCResultType - get the ISD::SETCC result ValueType
|
| /external/llvm/test/Transforms/ConstProp/ |
| 2002-09-03-SetCC-Bools.ll | 0 ; SetCC on boolean values was not implemented!
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 75 setTargetDAGCombine(ISD::SETCC);
281 if (Intr->getOpcode() == ISD::SETCC) {
283 SDNode *SetCC = Intr;
284 assert(SetCC->getConstantOperandVal(1) == 1);
285 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
287 Intr = SetCC->getOperand(0).getNode();
363 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
382 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
388 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
394 case ISD::SETCC:
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
397 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
[all...] |
| /external/icu4c/tools/gennorm2/ |
| n2builder.h | 59 void setCC(UChar32 c, uint8_t cc);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 70 /// which will be produced by a setcc instruction.
73 /// This serves most of the functions of the LLVM SETCC instruction, for two
81 SETCC,
|
| AArch64ISelLowering.cpp | 108 setOperationAction(ISD::SETCC, MVT::i32, Custom);
109 setOperationAction(ISD::SETCC, MVT::i64, Custom);
110 setOperationAction(ISD::SETCC, MVT::f32, Custom);
111 setOperationAction(ISD::SETCC, MVT::f64, Custom);
226 setOperationAction(ISD::SETCC, MVT::f128, Custom);
776 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2004-11-27-SetCCForCastLargerAndConstant.ll | 8 ; cast operands, and types of setCC operators. In all cases, the cast should
9 ; be eliminated. In many cases the setCC is also eliminated based on the
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 101 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
107 && "Unsupported setcc type!");
179 default: llvm_unreachable("Do not know how to soften this setcc!");
190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT),
193 NewLHS = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT), NewLHS,
[all...] |
| DAGCombiner.cpp | 540 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
541 // that selects between the values 1 and 0, making it equivalent to a setcc.
547 if (N.getOpcode() == ISD::SETCC) {
566 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| /external/v8/src/arm/ |
| code-stubs-arm.cc | 472 __ and_(exponent, source_, Operand(HeapNumber::kSignMask), SetCC);
705 __ and_(dst2, int_scratch, Operand(HeapNumber::kSignMask), SetCC);
707 __ rsb(int_scratch, int_scratch, Operand::Zero(), SetCC, mi);
726 __ sub(scratch2, dst1, Operand(HeapNumber::kMantissaBitsInTopWord), SetCC);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 32 SETCC,
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 332 /// Much like the scalar select and setcc, each bit in the condition selects
345 /// SetCC operator - This evaluates to a true value iff the condition is
351 SETCC,
502 /// compare, rather than as a combined SetCC node. The operands in order
[all...] |
