Lines Matching full:displacement
764 * Load value from base + displacement. Optionally perform null check
768 LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest,
773 bool thumb2Form = (displacement < 4092 && displacement >= 0);
775 int encoded_disp = displacement;
788 if (displacement <= 1020) {
794 if (displacement <= 1020) {
795 load = NewLIR4(kThumb2LdrdI8, r_dest, r_dest_hi, rBase, displacement >> 2);
797 load = LoadBaseDispBody(rBase, displacement, r_dest,
799 LoadBaseDispBody(rBase, displacement + 4, r_dest_hi,
808 if (displacement <= 1020) {
815 (displacement <= 1020) && (displacement >= 0)) {
820 (displacement <= 1020) && (displacement >= 0)) {
824 } else if (all_low_regs && displacement < 128 && displacement >= 0) {
825 DCHECK_EQ((displacement & 0x3), 0);
835 if (all_low_regs && displacement < 64 && displacement >= 0) {
836 DCHECK_EQ((displacement & 0x1), 0);
840 } else if (displacement < 4092 && displacement >= 0) {
852 if (all_low_regs && displacement < 32 && displacement >= 0) {
883 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, is64bit);
888 LIR* ArmMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest,
890 return LoadBaseDispBody(rBase, displacement, r_dest, -1, size, s_reg);
893 LIR* ArmMir2Lir::LoadBaseDispWide(int rBase, int displacement, int r_dest_lo,
895 return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg);
899 LIR* ArmMir2Lir::StoreBaseDispBody(int rBase, int displacement,
904 bool thumb2Form = (displacement < 4092 && displacement >= 0);
906 int encoded_disp = displacement;
914 if (displacement <= 1020) {
915 store = NewLIR4(kThumb2StrdI8, r_src, r_src_hi, rBase, displacement >> 2);
917 store = StoreBaseDispBody(rBase, displacement, r_src, -1, kWord);
918 StoreBaseDispBody(rBase, displacement + 4, r_src_hi, -1, kWord);
927 if (displacement <= 1020) {
938 if (displacement <= 1020) {
945 (displacement <= 1020) && (displacement >= 0)) {
949 } else if (all_low_regs && displacement < 128 && displacement >= 0) {
950 DCHECK_EQ((displacement & 0x3), 0);
961 if (all_low_regs && displacement < 64 && displacement >= 0) {
962 DCHECK_EQ((displacement & 0x1), 0);
973 if (all_low_regs && displacement < 32 && displacement >= 0) {
997 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, is64bit);
1002 LIR* ArmMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src,
1004 return StoreBaseDispBody(rBase, displacement, r_src, -1, size);
1007 LIR* ArmMir2Lir::StoreBaseDispWide(int rBase, int displacement,
1009 return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong);
1043 int displacement, int r_src, int r_src_hi, OpSize size,
1055 int displacement, int r_dest, int r_dest_hi, OpSize size,
