Lines Matching full:displacement
345 int displacement, int r_dest, int r_dest_hi, OpSize size,
370 DCHECK_EQ((displacement & 0x3), 0);
379 DCHECK_EQ((displacement & 0x3), 0);
383 DCHECK_EQ((displacement & 0x1), 0);
387 DCHECK_EQ((displacement & 0x1), 0);
401 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
405 displacement + HIWORD_OFFSET);
406 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
408 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
410 displacement + HIWORD_OFFSET);
414 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
417 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2,
424 displacement + LOWORD_OFFSET);
428 displacement + HIWORD_OFFSET);
430 displacement + LOWORD_OFFSET);
433 displacement + LOWORD_OFFSET);
435 displacement + HIWORD_OFFSET);
450 LIR* X86Mir2Lir::LoadBaseDisp(int rBase, int displacement,
452 return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
456 LIR* X86Mir2Lir::LoadBaseDispWide(int rBase, int displacement,
458 return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
463 int displacement, int r_src, int r_src_hi, OpSize size,
488 DCHECK_EQ((displacement & 0x3), 0);
497 DCHECK_EQ((displacement & 0x3), 0);
502 DCHECK_EQ((displacement & 0x1), 0);
514 store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src);
516 store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src);
517 store2 = NewLIR3(opcode, rBase, displacement + HIWORD_OFFSET, r_src_hi);
520 AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
523 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2,
530 displacement + LOWORD_OFFSET, r_src);
533 displacement + LOWORD_OFFSET, r_src);
535 displacement + HIWORD_OFFSET, r_src_hi);
549 LIR* X86Mir2Lir::StoreBaseDisp(int rBase, int displacement,
552 displacement, r_src, INVALID_REG, size,
556 LIR* X86Mir2Lir::StoreBaseDispWide(int rBase, int displacement,
558 return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
