Lines Matching refs:rn
141 Register rn,
150 static_cast<int32_t>(rn) << kRnShift |
261 void ArmAssembler::and_(Register rd, Register rn, ShifterOperand so,
263 EmitType01(cond, so.type(), AND, 0, rn, rd, so);
267 void ArmAssembler::eor(Register rd, Register rn, ShifterOperand so,
269 EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
273 void ArmAssembler::sub(Register rd, Register rn, ShifterOperand so,
275 EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
278 void ArmAssembler::rsb(Register rd, Register rn, ShifterOperand so,
280 EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
283 void ArmAssembler::rsbs(Register rd, Register rn, ShifterOperand so,
285 EmitType01(cond, so.type(), RSB, 1, rn, rd, so);
289 void ArmAssembler::add(Register rd, Register rn, ShifterOperand so,
291 EmitType01(cond, so.type(), ADD, 0, rn, rd, so);
295 void ArmAssembler::adds(Register rd, Register rn, ShifterOperand so,
297 EmitType01(cond, so.type(), ADD, 1, rn, rd, so);
301 void ArmAssembler::subs(Register rd, Register rn, ShifterOperand so,
303 EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
307 void ArmAssembler::adc(Register rd, Register rn, ShifterOperand so,
309 EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
313 void ArmAssembler::sbc(Register rd, Register rn, ShifterOperand so,
315 EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
319 void ArmAssembler::rsc(Register rd, Register rn, ShifterOperand so,
321 EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
325 void ArmAssembler::tst(Register rn, ShifterOperand so, Condition cond) {
326 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker.
327 EmitType01(cond, so.type(), TST, 1, rn, R0, so);
331 void ArmAssembler::teq(Register rn, ShifterOperand so, Condition cond) {
332 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker.
333 EmitType01(cond, so.type(), TEQ, 1, rn, R0, so);
337 void ArmAssembler::cmp(Register rn, ShifterOperand so, Condition cond) {
338 EmitType01(cond, so.type(), CMP, 1, rn, R0, so);
342 void ArmAssembler::cmn(Register rn, ShifterOperand so, Condition cond) {
343 EmitType01(cond, so.type(), CMN, 1, rn, R0, so);
347 void ArmAssembler::orr(Register rd, Register rn,
349 EmitType01(cond, so.type(), ORR, 0, rn, rd, so);
353 void ArmAssembler::orrs(Register rd, Register rn,
355 EmitType01(cond, so.type(), ORR, 1, rn, rd, so);
369 void ArmAssembler::bic(Register rd, Register rn, ShifterOperand so,
371 EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
418 Register rd, Register rn,
421 CHECK_NE(rn, kNoRegister);
427 (static_cast<int32_t>(rn) << kRnShift) |
436 void ArmAssembler::mul(Register rd, Register rn, Register rm, Condition cond) {
437 // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
438 EmitMulOp(cond, 0, R0, rd, rn, rm);
442 void ArmAssembler::mla(Register rd, Register rn, Register rm, Register ra,
444 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
445 EmitMulOp(cond, B21, ra, rd, rn, rm);
449 void ArmAssembler::mls(Register rd, Register rn, Register rm, Register ra,
451 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
452 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
456 void ArmAssembler::umull(Register rd_lo, Register rd_hi, Register rn,
458 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
459 EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
531 void ArmAssembler::ldrex(Register rt, Register rn, Condition cond) {
532 CHECK_NE(rn, kNoRegister);
539 (static_cast<int32_t>(rn) << kLdExRnShift) |
548 Register rn,
550 CHECK_NE(rn, kNoRegister);
557 (static_cast<int32_t>(rn) << kStrExRnShift) |
1129 void ArmAssembler::AddConstant(Register rd, Register rn, int32_t value,
1132 if (rd != rn) {
1133 mov(rd, ShifterOperand(rn), cond);
1142 add(rd, rn, shifter_op, cond);
1144 sub(rd, rn, shifter_op, cond);
1146 CHECK(rn != IP);
1149 add(rd, rn, ShifterOperand(IP), cond);
1152 sub(rd, rn, ShifterOperand(IP), cond);
1159 add(rd, rn, ShifterOperand(IP), cond);
1165 void ArmAssembler::AddConstantSetFlags(Register rd, Register rn, int32_t value,
1169 adds(rd, rn, shifter_op, cond);
1171 subs(rd, rn, shifter_op, cond);
1173 CHECK(rn != IP);
1176 adds(rd, rn, ShifterOperand(IP), cond);
1179 subs(rd, rn, ShifterOperand(IP), cond);
1186 adds(rd, rn, ShifterOperand(IP), cond);
