Lines Matching refs:xF
108 ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); }
129 explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {}
143 uint32_t rotate = ((instruction >> 8) & 0xf);
181 uint32_t cond = (instruction >> 28) & 0xf;
193 uint32_t imm4 = (instruction & 0xf);
199 args << ArmRegister(instruction & 0xf);
204 uint32_t op = (instruction >> 21) & 0xf;
231 if (rn.r == 0xf) {
350 // uint32_t op5 = (instr >> 4) & 0xF;
371 uint32_t op3 = (instr >> 21) & 0xF;
382 if (Rd.r != 0xF) {
395 if (Rn.r != 0xF) {
403 if (Rn.r != 0xF) {
410 if (Rd.r != 0xF) {
423 if (Rd.r != 0xF) {
437 if (Rd.r != 0xF) {
457 if (Rd.r != 0xF) {
460 if (Rn.r != 0xF) {
496 uint32_t coproc = (instr >> 8) & 0xF;
517 uint32_t Vd = (instr >> 12) & 0xF;
544 uint32_t opc1 = (instr >> 20) & 0xF;
545 uint32_t opc2 = (instr >> 16) & 0xF;
550 uint32_t Vd = (instr >> 12) & 0xF;
553 uint32_t Vm = instr & 0xF;
584 uint32_t Vd = (instr >> 12) & 0xF;
587 uint32_t Vm = instr & 0xF;
611 uint32_t op3 = (instr >> 21) & 0xF;
618 if (Rn.r == 0xF && (op3 == 0x2 || op3 == 0x3)) {
632 } else if (Rd.r == 0xF && S == 1 &&
682 if (Rn.r != 0xF) {
698 uint32_t Rn = (instr >> 16) & 0xF;
713 if (Rn.r != 0xF) {
736 // uint32_t op4 = (instr >> 8) & 0xF;
753 uint32_t cond = (instr >> 22) & 0xF;
762 uint32_t op5 = (instr >> 4) & 0xF;
789 uint32_t cond = (instr >> 22) & 0xF;
1008 uint32_t imm2 = (instr >> 4) & 0xF;
1070 case 0xC: case 0xD: case 0xE: case 0xF: {
1120 uint16_t opcode2 = (instr >> 6) & 0xF;
1161 case 0xC: case 0xD: case 0xE: case 0xF: {
1181 uint16_t opA = (instr >> 12) & 0xF;
1227 uint32_t cond = (instr >> 8) & 0xF;
1271 uint16_t opA = (instr >> 4) & 0xF;
1272 uint16_t opB = instr & 0xF;
