Lines Matching refs:PhysicalReg_ESP
226 load_effective_addr(-2, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
227 store_fpu_cw(false/*checkException*/, 0, PhysicalReg_ESP, true);
228 alu_binary_imm_mem(OpndSize_16, or_opc, 0xc00, 0, PhysicalReg_ESP, true);
229 load_fpu_cw(0, PhysicalReg_ESP, true);
230 alu_binary_imm_mem(OpndSize_16, xor_opc, 0xc00, 0, PhysicalReg_ESP, true);
233 load_fpu_cw(0, PhysicalReg_ESP, true);
234 load_effective_addr(2, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
310 load_effective_addr(-2, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
311 store_fpu_cw(false/*checkException*/, 0, PhysicalReg_ESP, true);
313 alu_binary_imm_mem(OpndSize_16, or_opc, 0xc00, 0, PhysicalReg_ESP, true);
315 load_fpu_cw(0, PhysicalReg_ESP, true);
317 alu_binary_imm_mem(OpndSize_16, xor_opc, 0xc00, 0, PhysicalReg_ESP, true);
321 load_fpu_cw(0, PhysicalReg_ESP, true);
322 load_effective_addr(2, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1309 load_effective_addr(-16, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1310 move_reg_to_mem(OpndSize_32, 1, false, 8, PhysicalReg_ESP, true);
1316 move_reg_to_mem(OpndSize_32, 2, false, 12, PhysicalReg_ESP, true);
1318 move_reg_to_mem(OpndSize_64, 1, false, 0, PhysicalReg_ESP, true);
1325 load_effective_addr(16, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1739 load_effective_addr(-8, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1740 move_reg_to_mem(OpndSize_32, 1, false, 0, PhysicalReg_ESP, true);
1741 move_reg_to_mem(OpndSize_32, 2, false, 4, PhysicalReg_ESP, true);
1744 load_effective_addr(8, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1778 load_effective_addr(-16, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
1779 move_reg_to_mem(OpndSize_64, 1, false, 0, PhysicalReg_ESP, true);
1780 move_reg_to_mem(OpndSize_64, 2, false, 8, PhysicalReg_ESP, true);
1783 load_effective_addr(16, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
