Lines Matching refs:stalls
83 "Transactions Eliminated");this.addComputeCycles("mali_hwc_COMPUTE_ACTIVE","Active");this.addComputeCounter("mali_hwc_COMPUTE_TASKS","Tasks");this.addComputeCounter("mali_hwc_COMPUTE_THREADS","Threads Started");this.addComputeCycles("mali_hwc_COMPUTE_CYCLES_DESC","Waiting for Descriptors");this.addTripipeCycles("mali_hwc_TRIPIPE_ACTIVE","Active");this.addArithCounter("mali_hwc_ARITH_WORDS","Instructions (/Pipes)");this.addArithCycles("mali_hwc_ARITH_CYCLES_REG","Reg scheduling stalls (/Pipes)");this.addArithCycles("mali_hwc_ARITH_CYCLES_L0",
84 "L0 cache miss stalls (/Pipes)");this.addArithCounter("mali_hwc_ARITH_FRAG_DEPEND","Frag dep check failures (/Pipes)");this.addLSCounter("mali_hwc_LS_WORDS","Instruction Words Completed");this.addLSCounter("mali_hwc_LS_ISSUES","Full Pipeline Issues");this.addLSCounter("mali_hwc_LS_RESTARTS","Restarts (unpairable insts)");this.addLSCounter("mali_hwc_LS_REISSUES_MISS","Pipeline reissue (cache miss/uTLB)");this.addLSCounter("mali_hwc_LS_REISSUES_VD","Pipeline reissue (varying data)");this.addLSCounter("mali_hwc_LS_REISSUE_ATTRIB_MISS",
92 "ExtRD (linefill)");this.addL2Counter("mali_hwc_L2_EXT_WRITE","External Write (ExtWR)");this.addL2Counter("mali_hwc_L2_EXT_WRITE_LINE","ExtWR (linefill)");this.addL2Counter("mali_hwc_L2_EXT_WRITE_SMALL","ExtWR (burst size <64B)");this.addL2Counter("mali_hwc_L2_EXT_BARRIER","External Barrier");this.addL2Counter("mali_hwc_L2_EXT_AR_STALL","Address Read stalls");this.addL2Counter("mali_hwc_L2_EXT_R_BUF_FULL","Response Buffer full stalls");this.addL2Counter("mali_hwc_L2_EXT_RD_BUF_FULL","Read Data Buffer full stalls");
93 this.addL2Counter("mali_hwc_L2_EXT_R_RAW","RAW hazard stalls");this.addL2Counter("mali_hwc_L2_EXT_W_STALL","Write Data stalls");this.addL2Counter("mali_hwc_L2_EXT_W_BUF_FULL","Write Data Buffer full");this.addL2Counter("mali_hwc_L2_EXT_R_W_HAZARD","WAW or WAR hazard stalls
