Lines Matching refs:Instr
300 Instr* pc = reinterpret_cast<Instr*>(pc_);
301 Instr* instr = reinterpret_cast<Instr*>(instructions);
303 *(pc + i) = *(instr + i);
460 const Instr kPopInstruction =
465 const Instr kPushRegPattern =
469 const Instr kPopRegPattern =
472 const Instr kMovLrPc = al | MOV | kRegister_pc_Code | kRegister_lr_Code * B12;
474 const Instr kLdrPCMask = 15 * B24 | 7 * B20 | 15 * B16;
475 const Instr kLdrPCPattern = 5 * B24 | L | kRegister_pc_Code * B16;
477 const Instr kVldrDPCMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8;
478 const Instr kVldrDPCPattern = 13 * B24 | L | kRegister_pc_Code * B16 | 11 * B8;
480 const Instr kBlxRegMask =
482 const Instr kBlxRegPattern =
484 const Instr kBlxIp = al | kBlxRegPattern | ip.code();
485 const Instr kMovMvnMask = 0x6d * B21 | 0xf * B16;
486 const Instr kMovMvnPattern = 0xd * B21;
487 const Instr kMovMvnFlip = B22;
488 const Instr kMovLeaveCCMask = 0xdff * B16;
489 const Instr kMovLeaveCCPattern = 0x1a0 * B16;
490 const Instr kMovwMask = 0xff * B20;
491 const Instr kMovwPattern = 0x30 * B20;
492 const Instr kMovwLeaveCCFlip = 0x5 * B21;
493 const Instr kCmpCmnMask = 0xdd * B20 | 0xf * B12;
494 const Instr kCmpCmnPattern = 0x15 * B20;
495 const Instr kCmpCmnFlip = B21;
496 const Instr kAddSubFlip = 0x6 * B21;
497 const Instr kAndBicFlip = 0xe * B21;
500 const Instr kLdrRegFpOffsetPattern =
502 const Instr kStrRegFpOffsetPattern =
504 const Instr kLdrRegFpNegOffsetPattern =
506 const Instr kStrRegFpNegOffsetPattern =
508 const Instr kLdrStrInstrTypeMask = 0xffff0000;
509 const Instr kLdrStrInstrArgumentMask = 0x0000ffff;
510 const Instr kLdrStrOffsetMask = 0x00000fff;
562 Condition Assembler::GetCondition(Instr instr) {
563 return Instruction::ConditionField(instr);
567 bool Assembler::IsBranch(Instr instr) {
568 return (instr & (B27 | B25)) == (B27 | B25);
572 int Assembler::GetBranchOffset(Instr instr) {
573 instr));
576 return ((instr & kImm24Mask) << 8) >> 6;
580 bool Assembler::IsLdrRegisterImmediate(Instr instr) {
581 return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20);
585 bool Assembler::IsVldrDRegisterImmediate(Instr instr) {
586 return (instr & (15 * B24 | 3 * B20 | 15 * B8)) == (13 * B24 | B20 | 11 * B8);
590 int Assembler::GetLdrRegisterImmediateOffset(Instr instr) {
591 ASSERT(IsLdrRegisterImmediate(instr));
592 bool positive = (instr & B23) == B23;
593 int offset = instr & kOff12Mask; // Zero extended offset.
598 int Assembler::GetVldrDRegisterImmediateOffset(Instr instr) {
599 ASSERT(IsVldrDRegisterImmediate(instr));
600 bool positive = (instr & B23) == B23;
601 int offset = instr & kOff8Mask; // Zero extended offset.
607 Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) {
608 ASSERT(IsLdrRegisterImmediate(instr));
613 instr = (instr & ~B23) | (positive ? B23 : 0);
615 return (instr & ~kOff12Mask) | offset;
619 Instr Assembler::SetVldrDRegisterImmediateOffset(Instr instr, int offset) {
620 ASSERT(IsVldrDRegisterImmediate(instr));
626 instr = (instr & ~B23) | (positive ? B23 : 0);
628 return (instr & ~kOff8Mask) | (offset >> 2);
632 bool Assembler::IsStrRegisterImmediate(Instr instr) {
633 return (instr & (B27 | B26 | B25 | B22 | B20)) == B26;
637 Instr Assembler::SetStrRegisterImmediateOffset(Instr instr, int offset) {
638 ASSERT(IsStrRegisterImmediate(instr));
643 instr = (instr & ~B23) | (positive ? B23 : 0);
645 return (instr & ~kOff12Mask) | offset;
649 bool Assembler::IsAddRegisterImmediate(Instr instr) {
650 return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23);
654 Instr Assembler::SetAddRegisterImmediateOffset(Instr instr, int offset) {
655 ASSERT(IsAddRegisterImmediate(instr));
659 return (instr & ~kOff12Mask) | offset;
663 Register Assembler::GetRd(Instr instr) {
665 reg.code_ = Instruction::RdValue(instr);
670 Register Assembler::GetRn(Instr instr) {
672 reg.code_ = Instruction::RnValue(instr);
677 Register Assembler::GetRm(Instr instr) {
679 reg.code_ = Instruction::RmValue(instr);
684 bool Assembler::IsPush(Instr instr) {
685 return ((instr & ~kRdMask) == kPushRegPattern);
689 bool Assembler::IsPop(Instr instr) {
690 return ((instr & ~kRdMask) == kPopRegPattern);
694 bool Assembler::IsStrRegFpOffset(Instr instr) {
695 return ((instr & kLdrStrInstrTypeMask) == kStrRegFpOffsetPattern);
699 bool Assembler::IsLdrRegFpOffset(Instr instr) {
700 return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpOffsetPattern);
704 bool Assembler::IsStrRegFpNegOffset(Instr instr) {
705 return ((instr & kLdrStrInstrTypeMask) == kStrRegFpNegOffsetPattern);
709 bool Assembler::IsLdrRegFpNegOffset(Instr instr) {
710 return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern);
714 bool Assembler::IsLdrPcImmediateOffset(Instr instr) {
717 return (instr & kLdrPCMask) == kLdrPCPattern;
721 bool Assembler::IsVldrDPcImmediateOffset(Instr instr) {
724 return (instr & kVldrDPCMask) == kVldrDPCPattern;
728 bool Assembler::IsTstImmediate(Instr instr) {
729 return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) ==
734 bool Assembler::IsCmpRegister(Instr instr) {
735 return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) ==
740 bool Assembler::IsCmpImmediate(Instr instr) {
741 return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) ==
746 Register Assembler::GetCmpImmediateRegister(Instr instr) {
747 ASSERT(IsCmpImmediate(instr));
748 return GetRn(instr);
752 int Assembler::GetCmpImmediateRawImmediate(Instr instr) {
753 ASSERT(IsCmpImmediate(instr));
754 return instr & kOff12Mask;
777 Instr instr = instr_at(pos);
778 if ((instr & ~kImm24Mask) == 0) {
780 return instr - (Code::kHeaderSize - kHeapObjectTag);
782 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
783 int imm26 = ((instr & kImm24Mask) << 8) >> 6;
784 if ((Instruction::ConditionField(instr) == kSpecialCondition) &&
785 ((instr & B24) != 0)) {
794 Instr instr = instr_at(pos);
795 if ((instr & ~kImm24Mask) == 0) {
803 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
804 if (Instruction::ConditionField(instr) == kSpecialCondition) {
807 instr = (instr & ~(B24 | kImm24Mask)) | ((imm26 & 2) >> 1)*B24;
810 instr &= ~kImm24Mask;
814 instr_at_put(pos, instr | (imm24 & kImm24Mask));
828 Instr instr = instr_at(l.pos());
829 if ((instr & ~kImm24Mask) == 0) {
832 ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx
833 Condition cond = Instruction::ConditionField(instr);
840 if ((instr & B24) != 0)
919 Instr* instr) {
931 if (instr != NULL) {
932 if ((*instr & kMovMvnMask) == kMovMvnPattern) {
934 *instr ^= kMovMvnFlip;
936 } else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) {
939 *instr ^= kMovwLeaveCCFlip;
940 *instr |= EncodeMovwImmediate(imm32);
946 } else if ((*instr & kCmpCmnMask) == kCmpCmnPattern) {
948 *instr ^= kCmpCmnFlip;
952 Instr alu_insn = (*instr & kALUMask);
956 *instr ^= kAddSubFlip;
962 *instr ^= kAndBicFlip;
1004 Instr instr) const {
1008 !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) {
1012 if ((instr & ~kCondMask) == 13*B21) { // mov, S not set
1052 void Assembler::addrmod1(Instr instr,
1057 ASSERT((instr & ~(kCondMask | kOpCodeMask | S)) == 0);
1063 !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) {
1069 Condition cond = Instruction::ConditionField(instr);
1070 if ((instr & ~kCondMask) == 13*B21) { // mov, S not set
1073 if ((instr & kMovMvnMask) == kMovMvnPattern) {
1085 addrmod1(instr, rn, rd, Operand(ip));
1089 instr |= I | rotate_imm*B8 | immed_8;
1092 instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
1096 instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code();
1098 emit(instr | rn.code()*B16 | rd.code()*B12);
1106 Instr instr, Register rd, const MemOperand& x) {
1107 ASSERT((instr & ~(kCondMask | B | L)) == B26);
1119 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1120 mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));
1121 addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_));
1125 instr |= offset_12;
1131 instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
1134 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
1138 void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
1139 ASSERT((instr & ~(kCondMask | L | S6 | H)) == (B4 | B7));
1152 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1153 mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));
1154 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
1158 instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf);
1162 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1164 Instruction::ConditionField(instr));
1165 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
1170 instr |= x.rm_.code();
1173 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
1177 void Assembler::addrmod4(Instr instr, Register rn, RegList rl) {
1178 ASSERT((instr & ~(kCondMask | P | U | W | L)) == B27);
1181 emit(instr | rn.code()*B16 | rl);
1185 void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {
1188 (instr & ~(kCondMask | kCoprocessorMask | P | U | N | W | L)));
1206 emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8);
1720 Instr instr;
1733 instr = I | rotate_imm*B8 | immed_8;
1736 instr = src.rm_.code();
1738 emit(cond | instr | B24 | B21 | fields | 15*B12);
1872 emit(reinterpret_cast<Instr>(msg));
2579 static Instr EncodeVCVT(const VFPType dst_type,
2963 bool Assembler::IsMovT(Instr instr) {
2964 instr &= ~(((kNumberOfConditions - 1) << 28) | // Mask off conditions
2967 return instr == 0x34*B20;
2971 bool Assembler::IsMovW(Instr instr) {
2972 instr &= ~(((kNumberOfConditions - 1) << 28) | // Mask off conditions
2975 return instr == 0x30*B20;
2979 bool Assembler::IsNop(Instr instr, int type) {
2982 return instr == (al | 13*B21 | type*B12 | type);
3289 Instr instr = instr_at(rinfo.pc());
3291 ASSERT((IsVldrDPcImmediateOffset(instr) &&
3292 GetVldrDRegisterImmediateOffset(instr) == 0));
3297 instr_at_put(rinfo.pc(), SetVldrDRegisterImmediateOffset(instr, delta));
3319 Instr instr = instr_at(rinfo.pc());
3322 ASSERT(!IsVldrDPcImmediateOffset(instr));
3330 if (IsLdrPcImmediateOffset(instr) &&
3331 GetLdrRegisterImmediateOffset(instr) == 0) {
3333 instr_at_put(rinfo.pc(), SetLdrRegisterImmediateOffset(instr, delta));
3336 ASSERT(IsMovW(instr));
