Lines Matching full:next
10 // CHECK-NEXT: [[T2:%.*]] = load i32* @uk
11 // CHECK-NEXT: [[T3:%.*]] = add i32 [[T1]], [[T2]]
12 // CHECK-NEXT: store i32 [[T3]], i32* @ui
16 // CHECK-NEXT: [[T2:%.*]] = load i32* @k
17 // CHECK-NEXT: [[T3:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T1]], i32 [[T2]])
18 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T3]], 0
19 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T3]], 1
20 // CHECK-NEXT: [[T6:%.*]] = xor i1 [[T5]], true
21 // CHECK-NEXT: br i1 [[T6]]
32 // CHECK-NEXT: [[T2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T1]], i32 1)
33 // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 0
34 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T2]], 1
35 // CHECK-NEXT: [[T5:%.*]] = xor i1 [[T4]], true
36 // CHECK-NEXT: br i1 [[T5]]
46 // CHECK-NEXT: [[T2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T1]], i32 1)
47 // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 0
48 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T2]], 1
49 // CHECK-NEXT: [[T5:%.*]] = xor i1 [[T4]], true
50 // CHECK-NEXT: br i1 [[T5]]
