Lines Matching full:next
21 // CHECK-NEXT: icmp uge i64 %[[SIZE]], 4
24 // CHECK-NEXT: %[[MISALIGN:.*]] = and i64 %[[PTRINT]], 3
25 // CHECK-NEXT: icmp eq i64 %[[MISALIGN]], 0
40 // CHECK-NEXT: icmp uge i64 %[[SIZE]], 24
43 // CHECK-NEXT: %[[MISALIGN:.*]] = and i64 %[[PTRINT]], 7
44 // CHECK-NEXT: icmp eq i64 %[[MISALIGN]], 0
49 // CHECK-NEXT: %[[VPTR:.*]] = load i64* %[[VPTRADDR]]
60 // CHECK-NEXT: xor i64 {{-4030275160588942838|2562089159}}, %[[VPTR]]
61 // CHECK-NEXT: mul i64 {{.*}}, -7070675565921424023
62 // CHECK-NEXT: lshr i64 {{.*}}, 47
63 // CHECK-NEXT: xor i64
64 // CHECK-NEXT: xor i64 %[[VPTR]]
65 // CHECK-NEXT: mul i64 {{.*}}, -7070675565921424023
66 // CHECK-NEXT: lshr i64 {{.*}}, 47
67 // CHECK-NEXT: xor i64
68 // CHECK-NEXT: %[[HASH:.*]] = mul i64 {{.*}}, -7070675565921424023
72 // CHECK-NEXT: %[[IDX:.*]] = and i64 %{{.*}}, 127
73 // CHECK-NEXT: getelementptr inbounds [128 x i64]* @__ubsan_vptr_type_cache, i32 0, i64 %[[IDX]]
74 // CHECK-NEXT: %[[CACHEVAL:.*]] = load i64*
75 // CHECK-NEXT: icmp eq i64 %[[CACHEVAL]], %[[HASH]]
76 // CHECK-NEXT: br i1
88 // CHECK-NEXT: icmp uge i64 %[[SIZE]], 4
91 // CHECK-NEXT: %[[MISALIGN:.*]] = and i64 %[[PTRINT]], 3
92 // CHECK-NEXT: icmp eq i64 %[[MISALIGN]], 0
100 // CHECK-NEXT: icmp uge i64 %[[SIZE]], 24
103 // CHECK-NEXT: %[[MISALIGN:.*]] = and i64 %[[PTRINT]], 7
104 // CHECK-NEXT: icmp eq i64 %[[MISALIGN]], 0
109 // CHECK-NEXT: xor i64 {{-4030275160588942838|2562089159}},
123 // CHECK-NEXT: br i1 %[[INBOUNDS]]
126 // CHECK-NEXT: %[[SHIFTED_OUT:.*]] = lshr i32 %[[LHS:.*]], %[[SHIFTED_OUT_WIDTH]]
130 // CHECK-NEXT: %[[SHIFTED_OUT_NOT_SIGN:.*]] = lshr i32 %[[SHIFTED_OUT]], 1
132 // CHECK-NEXT: %[[NO_OVERFLOW:.*]] = icmp eq i32 %[[SHIFTED_OUT_NOT_SIGN]], 0
135 // CHECK-NEXT: br i1 %[[VALID]]
141 // CHECK-NEXT: ret i32 %[[RET]]
148 // CHECK-NEXT: unreachable
