Lines Matching full:live
17 // Register live intervals: Registers must be defined only once, and must be
103 // Vregs that must be live in because they are used without being
111 // Regs defined in MBB and live out. Note that vregs passing through may
112 // be live out without being mentioned here.
175 // Live-out registers are either in regsLiveOut or vregsPassed.
499 // If this block has allocatable physical registers live-in, check that
507 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
673 report("MBB live-in list contains non-physical register", MBB);
965 *OS << "Live stack: " << LI << '\n';
969 *OS << "Live stack: " << LI << '\n';
1007 report("No live range at use", MO, MONum);
1008 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1012 report("Live range continues after kill flag", MO, MONum);
1025 report("No live range at use", MO, MONum);
1026 *OS << UseIdx << " is not live in " << LI << '\n';
1031 report("Live range continues after kill flag", MO, MONum);
1032 *OS << "Live range: " << LI << '\n';
1035 report("Virtual register has no live interval", MO, MONum);
1050 // We don't know which virtual registers are live in, so only complain
1052 // must be live in. PHI instructions are handled separately.
1074 // Check LiveInts for a live range, but only for virtual registers.
1089 report("No live range at def", MO, MONum);
1090 *OS << DefIdx << " is not live in " << LI << '\n';
1093 report("Virtual register has no Live interval", MO, MONum);
1139 // can pass through an MBB live, but may not be live every time. It is assumed
1142 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1180 // First push live-in regs to predecessors' vregsRequired.
1227 report("PHI operand is not live-out from predecessor",
1260 // Check for killed virtual registers that should be live out.
1268 report("Virtual register killed in block, but needed live out.", MFI);
1303 << " must be live through the block.\n";
1309 << " is not needed live through the block.\n";
1326 report("Missing live interval for virtual register", MF);
1350 report("Valno not live at def and not marked unused", MF, LI);
1356 report("Live range at def has different valno", MF, LI);
1358 << " where valno #" << DefVNI->id << " is live\n";
1428 assert(VNI && "Live range has no valno");
1431 report("Foreign valno in live range", MF, LI);
1436 report("Live range valno is marked unused", MF, LI);
1442 report("Bad start of live segment, no basic block", MF, LI);
1448 report("Live segment must begin at MBB entry or valno def", MBB, LI);
1455 report("Bad end of live segment, no basic block", MF, LI);
1460 // No more checks for live-out segments.
1469 // The live segment is ending inside EndMBB
1473 report("Live segment doesn't end at a valid instruction", EndMBB, LI);
1480 report("Live segment ends at B slot of an instruction", EndMBB, LI);
1488 report("Live segment ending at dead slot spans instructions", EndMBB, LI);
1493 // A live segment can only end at an early-clobber slot if it is being
1497 report("Live segment ending at early clobber slot must be "
1506 // A live range can end with either a redefinition, a kill flag on a
1527 report("Instruction ending live range doesn't read the register", MI);
1533 // Now check all the basic blocks in this live segment.
1535 // Is this live range the beginning of a non-PHIDef VN?
1537 // Not live-in to any blocks.
1558 // Check that VNI is live-out of all predecessors.
1564 // All predecessors must have a live-out value.
1566 report("Register not marked live out of predecessor", *PI, LI);
1567 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1568 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1575 report("Different value live out of predecessor", *PI, LI);
1576 *OS << "Valno #" << PVNI->id << " live out of BB#"
1578 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1601 report("Multiple connected components in live interval", MF, LI);
