Lines Matching full:live
268 // Update live variable information if there is any.
315 // IncomingReg's live interval.
330 // A dead PHI's live range begins and ends at the start of the MBB, but
334 assert(OrigDestVNI && "PHI destination should be live at block entry.");
341 // instruction from DestReg's live interval.
344 assert(DestVNI && "PHI destination should be live at its definition.");
403 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
409 // the copy we just inserted) is the last use of the source value. Live
411 // is live until the end of the block the PHI entry lives in. If the value
413 // have the value live-in.
415 // Okay, if we now know that the value is not live out of the block, we
476 // Definitions by other PHIs are not truly live-in for our purposes.
571 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
572 // when the source register is live-out for some other reason than a phi
580 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
584 // If Reg is not live-in to MBB, it means it must be live-in to some
588 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
633 // so that a register used only in a PHI is not live out of the block. In
635 // in the predecessor basic block, so that a register used only in a PHI is live
