Lines Matching full:issigned
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
103 unsigned NumOps, bool isSigned, SDLoc dl);
106 SDNode *Node, bool isSigned);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
1857 bool isSigned) {
1864 Entry.isSExt = isSigned;
1865 Entry.isZExt = !isSigned;
1887 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1905 bool isSigned, SDLoc dl) {
1913 Entry.isSExt = isSigned;
1914 Entry.isZExt = !isSigned;
1922 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1937 bool isSigned) {
1947 Entry.isSExt = isSigned;
1948 Entry.isZExt = !isSigned;
1956 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1983 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1998 return ExpandLibCall(LC, Node, isSigned);
2002 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2007 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2008 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2009 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2010 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2011 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2019 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2021 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2023 if (isSigned)
2049 bool isSigned = Opcode == ISD::SDIVREM;
2054 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2055 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2056 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2057 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2058 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2075 Entry.isSExt = isSigned;
2076 Entry.isZExt = !isSigned;
2084 Entry.isSExt = isSigned;
2085 Entry.isZExt = !isSigned;
2093 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2224 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2245 if (isSigned) {
2266 SDValue Bias = DAG.getConstantFP(isSigned ?
2286 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2287 // Code below here assumes !isSigned without checking again.
2319 if (!isSigned) {
2425 bool isSigned,
2442 if (isSigned) continue;
2456 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2467 bool isSigned,
3297 bool isSigned = Node->getOpcode() == ISD::SREM;
3298 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3299 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3303 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3306 useDivRem(Node, isSigned, false))) {
3314 } else if (isSigned)
3329 bool isSigned = Node->getOpcode() == ISD::SDIV;
3330 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3334 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3335 useDivRem(Node, isSigned, true)))
3338 else if (isSigned)
3461 bool isSigned = Node->getOpcode() == ISD::SMULO;
3462 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3464 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3465 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3466 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3471 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3472 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3507 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3518 if (isSigned) {
