Lines Matching defs:VTs
57 static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) {
58 SDVTList Res = {VTs, NumVTs};
332 ID.AddPointer(VTList.VTs);
1303 "Vector Shuffle VTs must be a vectors");
1305 && "Vector Shuffle VTs must have same element type");
2666 SDVTList VTs = getVTList(VT);
2670 AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
2675 N = new (NodeAllocator) UnarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, Operand);
2678 N = new (NodeAllocator) UnarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, Operand);
3075 "Extract subvector VTs must be a vectors!");
3077 "Extract subvector VTs must have the same element type!");
3238 SDVTList VTs = getVTList(VT);
3242 AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
3247 N = new (NodeAllocator) BinarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2);
3250 N = new (NodeAllocator) BinarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2);
3316 "Insert subvector VTs must be a vectors");
3343 SDVTList VTs = getVTList(VT);
3347 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
3352 N = new (NodeAllocator) TernarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2, N3);
3355 N = new (NodeAllocator) TernarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2, N3);
4119 SDVTList VTs = getVTList(VT, MVT::Other);
4123 AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
4130 SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl.getIROrder(), dl.getDebugLoc(), VTs, MemVT, Chain,
4191 SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
4196 AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
4203 SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl.getIROrder(), dl.getDebugLoc(), VTs, MemVT, Chain,
4250 SDVTList VTs = getVTList(VT, MVT::Other);
4254 AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
4261 SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl.getIROrder(), dl.getDebugLoc(), VTs, MemVT, Chain,
4274 SmallVector<EVT, 4> VTs;
4275 VTs.reserve(NumOps);
4277 VTs.push_back(Ops[i].getValueType());
4278 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
4284 const EVT *VTs, unsigned NumVTs,
4289 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
4332 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
4446 SDVTList VTs = Indexed ?
4450 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
4461 SDNode *N = new (NodeAllocator) LoadSDNode(Ops, dl.getIROrder(), dl.getDebugLoc(), VTs, AM, ExtType,
4537 SDVTList VTs = getVTList(MVT::Other);
4541 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4551 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl.getIROrder(), dl.getDebugLoc(), VTs, ISD::UNINDEXED,
4605 SDVTList VTs = getVTList(MVT::Other);
4609 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4619 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl.getIROrder(), dl.getDebugLoc(), VTs, ISD::UNINDEXED,
4632 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
4635 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4643 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl.getIROrder(), dl.getDebugLoc(), VTs, AM,
4708 SDVTList VTs = getVTList(VT);
4712 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
4718 N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, Ops, NumOps);
4721 N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, Ops, NumOps);
4739 const EVT *VTs, unsigned NumVTs,
4742 return getNode(Opcode, DL, VTs[0], Ops, NumOps);
4743 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
4749 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps);
4776 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
4856 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
4870 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
4871 I->VTs[2] == VT3)
4886 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
4887 I->VTs[2] == VT3 && I->VTs[3] == VT4)
4900 SDVTList SelectionDAG::getVTList(const EVT *VTs, unsigned NumVTs) {
4903 case 1: return getVTList(VTs[0]);
4904 case 2: return getVTList(VTs[0], VTs[1]);
4905 case 3: return getVTList(VTs[0], VTs[1], VTs[2]);
4906 case 4: return getVTList(VTs[0], VTs[1], VTs[2], VTs[3]);
4912 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1])
4915 if (std::equal(&VTs[2], &VTs[NumVTs], &I->VTs[2]))
4920 std::copy(VTs, VTs+NumVTs, Array);
5058 SDVTList VTs = getVTList(VT);
5059 return SelectNodeTo(N, MachineOpc, VTs, 0, 0);
5064 SDVTList VTs = getVTList(VT);
5066 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
5072 SDVTList VTs = getVTList(VT);
5074 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
5080 SDVTList VTs = getVTList(VT);
5082 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
5088 SDVTList VTs = getVTList(VT);
5089 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
5095 SDVTList VTs = getVTList(VT1, VT2);
5096 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
5101 SDVTList VTs = getVTList(VT1, VT2);
5102 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
5108 SDVTList VTs = getVTList(VT1, VT2, VT3);
5109 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
5115 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
5116 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
5122 SDVTList VTs = getVTList(VT1, VT2);
5124 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
5130 SDVTList VTs = getVTList(VT1, VT2);
5132 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2);
5139 SDVTList VTs = getVTList(VT1, VT2);
5141 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
5148 SDVTList VTs = getVTList(VT1, VT2, VT3);
5150 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3);
5154 SDVTList VTs, const SDValue *Ops,
5156 N = MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps);
5193 SDVTList VTs, const SDValue *Ops,
5197 if (VTs.VTs[VTs.NumVTs-1] != MVT::Glue) {
5199 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
5209 N->ValueList = VTs.VTs;
5210 N->NumValues = VTs.NumVTs;
5279 SDVTList VTs = getVTList(VT);
5280 return getMachineNode(Opcode, dl, VTs, None);
5285 SDVTList VTs = getVTList(VT);
5287 return getMachineNode(Opcode, dl, VTs, Ops);
5293 SDVTList VTs = getVTList(VT);
5295 return getMachineNode(Opcode, dl, VTs, Ops);
5301 SDVTList VTs = getVTList(VT);
5303 return getMachineNode(Opcode, dl, VTs, Ops);
5309 SDVTList VTs = getVTList(VT);
5310 return getMachineNode(Opcode, dl, VTs, Ops);
5315 SDVTList VTs = getVTList(VT1, VT2);
5316 return getMachineNode(Opcode, dl, VTs, None);
5322 SDVTList VTs = getVTList(VT1, VT2);
5324 return getMachineNode(Opcode, dl, VTs, Ops);
5330 SDVTList VTs = getVTList(VT1, VT2);
5332 return getMachineNode(Opcode, dl, VTs, Ops);
5339 SDVTList VTs = getVTList(VT1, VT2);
5341 return getMachineNode(Opcode, dl, VTs, Ops);
5348 SDVTList VTs = getVTList(VT1, VT2);
5349 return getMachineNode(Opcode, dl, VTs, Ops);
5356 SDVTList VTs = getVTList(VT1, VT2, VT3);
5358 return getMachineNode(Opcode, dl, VTs, Ops);
5365 SDVTList VTs = getVTList(VT1, VT2, VT3);
5367 return getMachineNode(Opcode, dl, VTs, Ops);
5374 SDVTList VTs = getVTList(VT1, VT2, VT3);
5375 return getMachineNode(Opcode, dl, VTs, Ops);
5382 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
5383 return getMachineNode(Opcode, dl, VTs, Ops);
5390 SDVTList VTs = getVTList(&ResultTys[0], ResultTys.size());
5391 return getMachineNode(Opcode, dl, VTs, Ops);
5395 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
5397 bool DoCSE = VTs.VTs[VTs.NumVTs-1] != MVT::Glue;
5405 AddNodeIDNode(ID, ~Opcode, VTs, Ops, NumOps);
5413 N = new (NodeAllocator) MachineSDNode(~Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
5462 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
5919 MemSDNode::MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
5921 : SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
5930 MemSDNode::MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
5933 : SDNode(Opc, Order, dl, VTs, Ops, NumOps),
5949 std::vector<EVT> VTs;
5952 VTs.reserve(MVT::LAST_VALUETYPE);
5954 VTs.push_back(MVT((MVT::SimpleValueType)i));
5972 return &SimpleVTArray->VTs[VT.getSimpleVT().SimpleTy];
