Lines Matching defs:HasBaseReg
234 bool HasBaseReg;
253 : BaseGV(0), BaseOffset(0), HasBaseReg(false), Scale(0), ScaledReg(0),
340 HasBaseReg = true;
346 HasBaseReg = true;
408 if (HasBaseReg && BaseRegs.empty()) {
410 OS << "**error: HasBaseReg**";
411 } else if (!HasBaseReg && !BaseRegs.empty()) {
413 OS << "**error: !HasBaseReg**";
1310 bool HasBaseReg, int64_t Scale) {
1313 return TTI.isLegalAddressingMode(AccessTy, BaseGV, BaseOffset, HasBaseReg, Scale);
1325 if (Scale != 0 && HasBaseReg && BaseOffset != 0)
1363 GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
1375 return isLegalUse(TTI, Kind, AccessTy, BaseGV, MinOffset, HasBaseReg,
1377 isLegalUse(TTI, Kind, AccessTy, BaseGV, MaxOffset, HasBaseReg, Scale);
1384 F.BaseOffset, F.HasBaseReg, F.Scale);
1408 F.BaseGV, F.BaseOffset, F.HasBaseReg, 1);
1424 F.HasBaseReg, F.Scale);
1428 F.HasBaseReg, F.Scale);
1450 bool HasBaseReg) {
1460 if (!HasBaseReg && Scale == 1) {
1462 HasBaseReg = true;
1465 return isLegalUse(TTI, Kind, AccessTy, BaseGV, BaseOffset, HasBaseReg, Scale);
1471 Type *AccessTy, const SCEV *S, bool HasBaseReg) {
1491 BaseOffset, HasBaseReg, Scale);
1653 bool reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg,
2104 /*HasBaseReg=*/ false, Scale))
2109 /*HasBaseReg=*/ false, Scale))
2166 LSRInstance::reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg,
2177 // Conservatively assume HasBaseReg is true for now.
2180 LU.MaxOffset - NewOffset, HasBaseReg))
2185 NewOffset - LU.MinOffset, HasBaseReg))
2215 Offset, /*HasBaseReg=*/ true)) {
2226 if (reconcileNewOffset(LU, Offset, /*HasBaseReg=*/true, Kind, AccessTy))
3002 F.HasBaseReg = true;
3444 Base.HasBaseReg = Base.BaseRegs.size() > 1;
3461 !Base.HasBaseReg && Base.BaseOffset == 0 && !Base.BaseGV)
3959 if (!reconcileNewOffset(*LUThatHas, F.BaseOffset, /*HasBaseReg=*/ false,
