Lines Matching refs:tblgen_source_dir
26 tblgen_source_dir := $(LOCAL_PATH)
28 tblgen_source_dir := $(TBLGEN_TD_DIR)
31 ifneq (,$(filter $(tblgen_source_dir),MCTargetDesc))
32 tblgen_td_deps := $(tblgen_source_dir)/../*.td
34 tblgen_td_deps := $(tblgen_source_dir)/*.td
41 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc)
43 $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
48 $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
53 $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
58 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc)
60 $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
65 $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
70 $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
75 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/Mips/MCTargetDesc)
77 $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
82 $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
87 $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
95 $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
102 $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
109 $(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
116 $(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
123 $(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
130 $(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
137 $(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
144 $(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
151 $(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
158 $(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
165 $(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
172 $(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
179 $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
186 $(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
193 $(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \
200 $(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
