Lines Matching full:arm
2 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=ARM
3 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6t2 | FileCheck %s -check-prefix=MOVT
15 ; ARM-LABEL: t:
16 ; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
17 ; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
21 ; ARM: ldr r{{[0-9]+}}, LCPI0_1
22 ; ARM: LPC0_0:
23 ; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
24 ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
38 ; ARM: LCPI0_0:
39 ; ARM: LCPI0_1:
40 ; ARM: .section
