Lines Matching full:next
13 ; CHECK-NEXT: ret i32
23 ; CHECK-NEXT: xor i32
24 ; CHECK-NEXT: ret i32
34 ; CHECK-NEXT: ret i32
44 ; CHECK-NEXT: xor i32
45 ; CHECK-NEXT: ret i32
64 ; CHECK-NEXT: ashr i32 %a, 31
65 ; CHECK-NEXT: %f = and i32 %e, %b
66 ; CHECK-NEXT: ret i32 %f
124 ; CHECK-NEXT: = xor i1 %A, true
125 ; CHECK-NEXT: ret i1
167 ; CHECK-NEXT: %cmp = icmp ne i32 %x, 3
177 ; CHECK-NEXT: %cmp = icmp ne i32 %x, 3
186 ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3
195 ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3
499 ; CHECK-NEXT: and i32 %x1, 16711935
500 ; CHECK-NEXT: icmp eq i32 {{.*}}, 4980863
501 ; CHECK-NEXT: ret i1
515 ; CHECK-NEXT: ashr exact
516 ; CHECK-NEXT: ashr
517 ; CHECK-NEXT: icmp
526 ; CHECK-NEXT: %and = and i8 %a, -64
527 ; CHECK-NEXT: icmp eq i8 %and, -128
536 ; CHECK-NEXT: icmp eq i32 %a, -123
544 ; CHECK-NEXT: icmp eq i32 %a, -113
565 ; CHECK-NEXT: icmp ne
575 ; CHECK-NEXT: icmp ne
585 ; CHECK-NEXT: call i32 @test58_d(i64 36029346783166592)
614 ; CHECK-NEXT: %gep1.idx = shl nuw i64 %i, 2
615 ; CHECK-NEXT: icmp slt i64 %gep1.idx, %j
616 ; CHECK-NEXT: ret i1
629 ; CHECK-NEXT: ret i1
638 ; CHECK-NEXT: ret i1 true
647 ; CHECK-NEXT: %1 = trunc i32 %b to i8
648 ; CHECK-NEXT: %c = icmp eq i8 %1, %a
649 ; CHECK-NEXT: ret i1 %c
658 ; CHECK-NEXT: %1 = trunc i32 %b to i8
659 ; CHECK-NEXT: %c = icmp eq i8 %1, %a
660 ; CHECK-NEXT: ret i1 %c
668 ; CHECK-NEXT: ret i1 true
677 ; CHECK-NEXT: ret i1 true
712 ; CHECK-NEXT: %A = srem i32 5, %X
713 ; CHECK-NEXT: %C = icmp ne i32 %A, 2
714 ; CHECK-NEXT: ret i1 %C
723 ; CHECK-NEXT: %1 = trunc i32 %x to i16
724 ; CHECK-NEXT: %cmp = icmp slt i16 %1, 36
733 ; CHECK-NEXT: %1 = trunc i32 %x to i8
734 ; CHECK-NEXT: %cmp = icmp slt i8 %1, 36
743 ; CHECK-NEXT: %1 = trunc i32 %x to i16
744 ; CHECK-NEXT: %cmp = icmp slt i16 %1, 36
752 ; CHECK-NEXT: %1 = trunc i32 %x to i8
753 ; CHECK-NEXT: %cmp = icmp slt i8 %1, 36
763 ; CHECK-NEXT: icmp sgt i32 %x, 0
771 ; CHECK-NEXT: icmp sgt i32 %x, -1
779 ; CHECK-NEXT: icmp sgt i32 %x, 0
788 ; CHECK-NEXT: icmp eq i32 %x, 0
804 ; CHECK-NEXT: icmp ne i32 %x, 0
822 ; CHECK-NEXT: icmp sgt i32 %x, 0
830 ; CHECK-NEXT: icmp slt i32 %x, 0
838 ; CHECK-NEXT: icmp slt i32 %x, 1
846 ; CHECK-NEXT: icmp slt i32 %x, 0
862 ; CHECK-NEXT: %mul = mul i32 %x, -12
871 ; CHECK-NEXT: icmp ne i32 %x, 0
879 ; CHECK-NEXT: icmp eq i32 %x, 0
887 ; CHECK-NEXT: ret i1 true
895 ; CHECK-NEXT: ret i1 false
903 ; CHECK-NEXT: icmp sgt i32 %x, %y
911 ; CHECK-NEXT: icmp sge i32 %x, %y
919 ; CHECK-NEXT: icmp sle i32 %x, %y
927 ; CHECK-NEXT: icmp slt i32 %x, %y
935 ; CHECK-NEXT: [[ADD:%[a-z0-9]+]] = add nsw i32 %y, 37
936 ; CHECK-NEXT: icmp sle i32 [[ADD]], %x
945 ; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = add nsw i32 %x, -37
946 ; CHECK-NEXT: icmp sge i32 [[SUB]], %y
955 ; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B
956 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A
957 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 0
958 ; CHECK-NEXT: ret i1 [[CMP]]
968 ; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B
969 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A
970 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 0
971 ; CHECK-NEXT: ret i1 [[CMP]]
981 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, 240
982 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 224
983 ; CHECK-NEXT: ret i1 [[CMP]]
994 ; CHECK-NEXT: ret i1 false
1003 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %V, 5
1004 ; CHECK-NEXT: ret i1 [[CMP]]
1012 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 %V, 5
1013 ; CHECK-NEXT: ret i1 [[CMP]]
1021 ; CHECK-NEXT: ret i1 false
1029 ; CHECK-NEXT: ret i1 true
1037 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %V, 5
1038 ; CHECK-NEXT: ret i1 [[CMP]]
1046 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %V, 4
1047 ; CHECK-NEXT: ret i1 [[CMP]]
1055 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %V, 5
1056 ; CHECK-NEXT: ret i1 [[CMP]]
1064 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %V, 4
1065 ; CHECK-NEXT: ret i1 [[CMP]]
1073 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 %V, 31
1074 ; CHECK-NEXT: ret i1 [[CMP]]
1082 ; CHECK-NEXT: ret i1 false
1090 ; CHECK-NEXT: ret i1 true
1098 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %V, 31
1099 ; CHECK-NEXT: ret i1 [[CMP]]
1107 ; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = add i64 %b, -1
1108 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp uge i64 [[SUB]], %a
1109 ; CHECK-NEXT: ret i1 [[CMP]]
1118 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
1119 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 14
1120 ; CHECK-NEXT: ret i1 [[CMP]]
1128 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
1129 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 14
1130 ; CHECK-NEXT: ret i1 [[CMP]]
1138 ; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %X, 1
1139 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[OR]], 3
1140 ; CHECK-NEXT: ret i1 [[CMP]]
1148 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
1149 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 14
1150 ; CHECK-NEXT: ret i1 [[CMP]]
1158 ; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %X, 1
1159 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[OR]], 3
1160 ; CHECK-NEXT: ret i1 [[CMP]]
1168 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %X, -17
1169 ; CHECK-NEXT: ret i1 [[CMP]]
1177 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %X, -16
1178 ; CHECK-NEXT: ret i1 [[CMP]]
1186 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %X, -5
1187 ; CHECK-NEXT: ret i1 [[CMP]]
1195 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %X, -4
1196 ; CHECK-NEXT: ret i1 [[CMP]]
