Lines Matching full:next
8 ; CHECK-NEXT: ret i32 0
15 ; CHECK-NEXT: ret i32 0
22 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
23 ; CHECK-NEXT: ret i32 [[AND]]
30 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
31 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
32 ; CHECK-NEXT: ret i1 [[CMP]]
40 ; CHECK-NEXT: [[SEL:%.*]] = select i1 %C, i32 0, i32 7
41 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SEL]], %X
49 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 %B to i32
50 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 32, [[ZEXT]]
51 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
52 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %X
53 ; CHECK-NEXT: ret i32 [[AND]]
62 ; CHECK-NEXT: ret i32 undef
69 ; CHECK-NEXT: ret i32 0
77 ; CHECK-NEXT: ret i32 0
85 ; CHECK-NEXT: ret i32 0
93 ; CHECK-NEXT: ret i32 0
104 ; CHECK-NEXT: ret i32 0
113 ; CHECK-NEXT: ret i32 0
121 ; CHECK-NEXT: ret i32 0
128 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
129 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
130 ; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ZEXT]], -1
131 ; CHECK-NEXT: [[AND:%.*]] = and i64 [[ADD]], %x
132 ; CHECK-NEXT: ret i64 [[AND]]
141 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
142 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
143 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %x
144 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[AND]] to i64
145 ; CHECK-NEXT: ret i64 [[ZEXT]]
155 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %y, 11
156 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 4
157 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], 3
158 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[OR]], %x
159 ; CHECK-NEXT: ret i32 [[REM]]
169 ; CHECK-NEXT: icmp ne i32 %X, 1
170 ; CHECK-NEXT: zext i1
171 ; CHECK-NEXT: ret
178 ; CHECK-NEXT: [[AND:%.*]] = and i16 %x, 4
179 ; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[AND]] to i32
180 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i32 [[EXT]], 3
181 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], 63
182 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[XOR]], %y
183 ; CHECK-NEXT: ret i32 [[REM]]
193 ; CHECK-NEXT: [[SHL1:%.*]] = shl i32 1, %x
194 ; CHECK-NEXT: [[SHL2:%.*]] = shl i32 1, %y
195 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL1]], [[SHL2]]
196 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[AND]], [[SHL1]]
197 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], -1
198 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[SUB]], %y
199 ; CHECK-NEXT: ret i32 [[REM]]
