Lines Matching refs:Registers
47 // Are all super-registers containing this SubRegIndex covered by their
48 // sub-registers?
128 // Lazily compute a map of all sub-registers.
129 // This includes unique entries for all sub-sub-registers.
132 // Compute extra sub-registers by combining the existing sub-registers.
135 // Add this as a super-register to all sub-registers after the sub-register
140 assert(SubRegsComplete && "Must precompute sub-registers");
144 // Add sub-registers to OSet following a pre-order defined by the .td file.
156 // Get the list of super-registers in topological order, small to large.
157 // This is valid after computeSubRegs visits all registers during RegBank
160 assert(SubRegsComplete && "Must precompute sub-registers");
165 // contains all registers in 'Aliases', and all registers that mention this
172 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
174 // sub-register indices mapping to the same kind of sub-registers
224 // The sub-registers explicit in the .td file form a tree.
231 // Super-registers where this is the first explicit sub-register.
243 // Allocation orders. Order[0] always contains all registers in Members.
258 // registers have a SubRegIndex sub-register.
269 // Bit vector of TopoSigs for the registers in this class. This will be
306 // 1. All RC registers are also in this.
315 // registers have a SubIdx sub-register.
327 // containing only SubIdx super-registers of this class.
330 // addSuperRegClass - Add a class containing only SudIdx super-registers.
348 // The order of registers is the same as in the .td file.
357 // Get the set of registers. This set contains the same registers as
403 // registers overlap if and only if they have a register unit in common.
406 // registers inherit the units of their sub-registers.
413 // Each native RegUnit corresponds to one or two root registers. The full
414 // set of registers containing this unit can be computed as the union of
415 // these two registers and their super-registers.
446 // CodeGenRegBank - Represent a target's registers and the relations between
461 // Registers.
462 std::vector<CodeGenRegister*> Registers;
530 // in the .td files. The rest are synthesized such that all sub-registers
552 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
560 // Get a Register's index into the Registers array.
566 // leaf registers is allocated number 0.
579 // registers.
661 // weight of the register. An exact solution requires all registers in a
670 // Compute the set of registers completely covered by the registers in Regs.
672 // all sub-registers, and all super-registers that are covered by the
673 // registers in Regs.
675 // This is used to compute the mask of call-preserved registers from a list
679 // Bit mask of lanes that cover their registers. A sub-register index whose
