Lines Matching refs:Writes
190 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
209 // Reserve idx=0 for invalid writes/reads.
282 // itinerary resources. Index reads and writes in separate domains.
298 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
333 /// Compute a SchedWrite name from a sequence of writes.
388 IdxVec &Writes, IdxVec &Reads) const {
392 findRWs(WriteDefs, Writes, false);
464 // Find the existing SchedWrite that models this sequence of writes.
515 IdxVec Writes, Reads;
517 findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
522 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
558 if (!SC.Writes.empty()) {
561 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; ++WI)
574 IdxVec Writes;
577 Writes, Reads);
578 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
596 const IdxVec &Writes,
600 && I->Writes == Writes && I->Reads == Reads) {
669 SC.Writes = OperWrites;
742 // Preserve ItinDef and Writes/Reads for processors without an InstRW entry.
744 SC.Writes = SchedClasses[OldSCIdx].Writes;
857 if (!SchedClasses[Idx].Writes.empty()) {
858 inferFromRW(SchedClasses[Idx].Writes, SchedClasses[Idx].Reads,
883 IdxVec Writes, Reads;
884 findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
886 inferFromRW(Writes, Reads, FromClassIdx, ProcIndices);
906 IdxVec Writes, Reads;
907 findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
910 inferFromRW(Writes, Reads, SCIdx, ProcIndices); // May mutate SchedClasses.
1143 // Push the Reads/Writes selected by this variant onto the PredTransition
1212 // RWSeq is a sequence of all Reads or all Writes for the next read or write
1252 // Read/Writes guarded by the variant. This is exponential in the number of
1253 // variant Read/Writes, but in practice detection of mutually exclusive
1372 // Iterate until no variant writes remain.
1459 IdxVec Writes, Reads;
1461 Writes, Reads);
1462 collectRWResources(Writes, Reads, ProcIndices);
1465 collectRWResources(SCI->Writes, SCI->Reads, SCI->ProcIndices);
1545 IdxVec Writes, Reads;
1546 findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
1548 collectRWResources(Writes, Reads, ProcIndices);
1580 assert(AliasRW.IsRead == IsRead && "cannot alias reads to writes");
1592 void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
1596 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
1728 << " Writes: ";
1729 for (unsigned i = 0, N = Writes.size(); i < N; ++i) {
1730 SchedModels->getSchedWrite(Writes[i]).dump();
