Lines Matching refs:OS
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
69 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
78 emitSourceFileHeader("Target Register Enum Values", OS);
80 OS << "\n#ifdef GET_REGINFO_ENUM\n";
81 OS << "#undef GET_REGINFO_ENUM\n";
83 OS << "namespace llvm {\n\n";
85 OS << "class MCRegisterClass;\n"
90 OS << "namespace " << Namespace << " {\n";
91 OS << "enum {\n NoRegister,\n";
94 OS << " " << Registers[i]->getName() << " = " <<
98 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
99 OS << "};\n";
101 OS << "}\n";
110 OS << "\n// Register classes\n";
112 OS << "namespace " << Namespace << " {\n";
113 OS << "enum {\n";
115 if (i) OS << ",\n";
116 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
117 OS << " = " << i;
119 OS << "\n };\n";
121 OS << "}\n";
128 OS << "\n// Register alternate name indices\n";
130 OS << "namespace " << Namespace << " {\n";
131 OS << "enum {\n";
133 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
134 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
135 OS << "};\n";
137 OS << "}\n";
142 OS << "\n// Subregister indices\n";
146 OS << "namespace " << Namespace << " {\n";
147 OS << "enum {\n NoSubRegister,\n";
149 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
150 OS << " NUM_TARGET_SUBREGS\n};\n";
152 OS << "}\n";
155 OS << "} // End llvm namespace \n";
156 OS << "#endif // GET_REGINFO_ENUM\n\n";
160 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
165 OS << "/// Get the weight in units of pressure for this register class.\n"
173 OS << " {0, 0";
177 OS << " {" << (*Regs.begin())->getWeight(RegBank)
180 OS << "}, \t// " << RC.getName() << "\n";
182 OS << " {0, 0} };\n"
194 OS << "/// Get the weight in units of pressure for this register unit.\n"
200 OS << " static const uint8_t RUWeightTable[] = {\n ";
205 OS << RU.Weight << ", ";
207 OS << "0 };\n"
211 OS << " // All register units have unit weight.\n"
214 OS << "}\n\n";
216 OS << "\n"
221 OS << "// Get the name of this register unit pressure set.\n"
226 OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
228 OS << " 0 };\n"
232 OS << "// Get the register unit pressure limit for this dimension.\n"
239 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
242 OS << " 0 };\n"
249 OS << "/// Table of pressure sets per register class or unit.\n"
263 OS << PSets[j] << ", ";
266 OS << "-1, \t// #" << RCSetStarts[i] << " ";
268 OS << RegBank.getRegClasses()[i]->getName();
270 OS << "inferred";
273 OS << "~" << RegBank.getRegSetAt(*PSetI).Name;
276 OS << "\n ";
279 OS << "-1 };\n\n";
281 OS << "/// Get the dimensions of register pressure impacted by this "
286 OS << " static const unsigned RCSetStartTable[] = {\n ";
288 OS << RCSetStarts[i] << ",";
290 OS << "0 };\n"
295 OS << "/// Get the dimensions of register pressure impacted by this "
302 OS << " static const unsigned RUSetStartTable[] = {\n ";
305 OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ",";
307 OS << "0 };\n"
314 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
344 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
349 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
350 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
351 OS << i << "Dwarf2L[]";
354 OS << " = {\n";
369 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
372 OS << "};\n";
374 OS << ";\n";
379 OS << "extern const unsigned " << Namespace
382 OS << " = sizeof(" << Namespace
386 OS << ";\n\n";
404 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
405 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
406 OS << i << "L2Dwarf[]";
408 OS << " = {\n";
417 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
420 OS << "};\n";
422 OS << ";\n";
427 OS << "extern const unsigned " << Namespace
430 OS << " = sizeof(" << Namespace
434 OS << ";\n\n";
440 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
459 OS << " switch (";
461 OS << "DwarfFlavour";
463 OS << "EHFlavour";
464 OS << ") {\n"
469 OS << " case " << i << ":\n";
470 OS << " ";
472 OS << "RI->";
477 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
479 OS << "false";
481 OS << "true";
482 OS << ");\n";
483 OS << " break;\n";
485 OS << " }\n";
490 OS << " switch (";
492 OS << "DwarfFlavour";
494 OS << "EHFlavour";
495 OS << ") {\n"
500 OS << " case " << i << ":\n";
501 OS << " ";
503 OS << "RI->";
508 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
510 OS << "false";
512 OS << "true";
513 OS << ");\n";
514 OS << " break;\n";
516 OS << " }\n";
522 static void printBitVectorAsHex(raw_ostream &OS,
531 OS << format("0x%0*x, ", Digits, Value);
545 void print(raw_ostream &OS) {
546 printBitVectorAsHex(OS, Values, 8);
550 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
551 OS << getEnumName(VT);
554 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
555 OS << Idx->EnumValue;
597 static void printDiff16(raw_ostream &OS, uint16_t Val) {
598 OS << Val;
630 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
634 OS << "unsigned " << ClName
667 OS << " static const " << getMinimalTypeForRange(Rows.size())
670 OS << RowMap[i] << ", ";
671 OS << "\n };\n";
675 OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1)
678 OS << " { ";
681 OS << Rows[r][i]->EnumValue << ", ";
683 OS << "0, ";
684 OS << "},\n";
686 OS << " };\n\n";
688 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n"
691 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
693 OS << " return Rows[0][IdxB];\n";
694 OS << "}\n\n";
701 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
703 emitSourceFileHeader("MC Register Information", OS);
705 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
706 OS << "#undef GET_REGINFO_MC_DESC\n";
784 OS << "namespace llvm {\n\n";
789 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
790 DiffSeqs.emit(OS, printDiff16);
791 OS << "};\n\n";
794 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
795 SubRegIdxSeqs.emit(OS, printSubRegIndex);
796 OS << "};\n\n";
799 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
801 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
805 OS << " { " << (*SRI)->Offset << ", "
809 OS << "};\n\n";
813 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
814 RegStrings.emit(OS, printChar);
815 OS << "};\n\n";
817 OS << "extern const MCRegisterDesc " << TargetName
819 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
824 OS << " { " << RegStrings.get(Reg->getName()) << ", "
830 OS << "};\n\n"; // End of register descriptors...
834 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n";
839 OS << " { " << getQualifiedName(Roots.front()->TheDef);
841 OS << ", " << getQualifiedName(Roots[r]->TheDef);
842 OS << " },\n";
844 OS << "};\n\n";
849 OS << "namespace { // Register classes...\n";
860 OS << " // " << Name << " Register Class...\n"
865 OS << getQualifiedName(Reg) << ", ";
867 OS << "\n };\n\n";
869 OS << " // " << Name << " Bit set.\n"
877 BVE.print(OS);
878 OS << "\n };\n\n";
881 OS << "}\n\n";
883 OS << "extern const MCRegisterClass " << TargetName
895 OS << " { " << '\"' << RC.getName() << "\", "
905 OS << "};\n\n";
907 EmitRegMappingTables(OS, Regs, false);
910 OS << "extern const uint16_t " << TargetName;
911 OS << "RegEncodingTable[] = {\n";
913 OS << " 0,\n";
922 OS << " " << Value << ",\n";
924 OS << "};\n"; // End of HW encoding table
927 OS << "static inline void Init" << TargetName
942 EmitRegMapping(OS, Regs, false);
944 OS << "}\n\n";
946 OS << "} // End llvm namespace \n";
947 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
951 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
953 emitSourceFileHeader("Register Information Header Fragment", OS);
955 OS << "\n#ifdef GET_REGINFO_HEADER\n";
956 OS << "#undef GET_REGINFO_HEADER\n";
961 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
963 OS << "namespace llvm {\n\n";
965 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
971 OS << " virtual unsigned composeSubRegIndicesImpl"
976 OS << " virtual const RegClassWeight &getRegClassWeight("
990 OS << "namespace " << RegisterClasses[0]->Namespace
998 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1000 OS << "} // end of namespace " << TargetName << "\n\n";
1002 OS << "} // End llvm namespace \n";
1003 OS << "#endif // GET_REGINFO_HEADER\n\n";
1010 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1012 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1014 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1015 OS << "#undef GET_REGINFO_TARGET_DESC\n";
1017 OS << "namespace llvm {\n\n";
1020 OS << "extern const MCRegisterClass " << Target.getName()
1044 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1045 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1046 OS << "};\n";
1049 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1051 OS << SubRegIndices[i]->getName();
1053 OS << "\", \"";
1055 OS << "\" };\n\n";
1058 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1060 OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask)
1063 OS << " };\n\n";
1065 OS << "\n";
1069 OS << "\nstatic const TargetRegisterClass *const "
1098 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1099 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1111 OS << "\n ";
1112 printBitVectorAsHex(OS, MaskBV, 32);
1113 OS << "// " << Idx->getName();
1116 OS << "\n};\n\n";
1119 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1121 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1122 OS << "};\n\n";
1133 OS << "static const TargetRegisterClass *const "
1136 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
1137 OS << " NULL\n};\n\n";
1144 OS << "\nstatic inline unsigned " << RC.getName()
1152 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1154 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1155 OS << " };\n";
1158 OS << " const MCRegisterClass &MCR = " << Target.getName()
1164 OS << "),\n ArrayRef<MCPhysReg>(";
1166 OS << "),\n makeArrayRef(AltOrder" << oi;
1167 OS << ")\n };\n const unsigned Select = " << RC.getName()
1174 OS << "namespace " << RegisterClasses[0]->Namespace
1179 OS << " extern const TargetRegisterClass "
1187 OS << "NullRegClasses,\n ";
1189 OS << RC.getName() << "Superclasses,\n ";
1191 OS << "0\n";
1193 OS << RC.getName() << "GetRawAllocationOrder\n";
1194 OS << " };\n\n";
1197 OS << "}\n";
1200 OS << "\nnamespace {\n";
1201 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1203 OS << " &" << RegisterClasses[i]->getQualifiedName()
1205 OS << " };\n";
1206 OS << "}\n"; // End of anonymous namespace...
1210 OS << "\nstatic const TargetRegisterInfoDesc "
1212 OS << " { 0, 0 },\n";
1217 OS << " { ";
1218 OS << Reg.CostPerUse << ", "
1221 OS << "};\n"; // End of register descriptors...
1227 emitComposeSubRegIndices(OS, RegBank, ClassName);
1231 OS << "const TargetRegisterClass *" << ClassName
1237 OS << " static const uint8_t Table[";
1239 OS << " static const uint16_t Table[";
1242 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
1245 OS << " {\t// " << RC.getName() << "\n";
1249 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
1252 OS << " 0,\t// " << Idx->getName() << "\n";
1254 OS << " },\n";
1256 OS << " };\n assert(RC && \"Missing regclass\");\n"
1263 EmitRegUnitPressure(OS, RegBank, ClassName);
1266 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1267 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1268 OS << "extern const char " << TargetName << "RegStrings[];\n";
1269 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n";
1270 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1271 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1273 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1275 EmitRegMappingTables(OS, Regs, true);
1277 OS << ClassName << "::\n" << ClassName
1282 OS.write_hex(RegBank.CoveringLanes);
1283 OS << ") {\n"
1296 EmitRegMapping(OS, Regs, true);
1298 OS << "}\n\n";
1310 OS << "static const MCPhysReg " << CSRSet->getName()
1313 OS << getQualifiedName((*Regs)[r]) << ", ";
1314 OS << "0 };\n";
1317 OS << "static const uint32_t " << CSRSet->getName()
1319 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1320 OS << "};\n";
1322 OS << "\n\n";
1324 OS << "} // End llvm namespace \n";
1325 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1328 void RegisterInfoEmitter::run(raw_ostream &OS) {
1333 runEnums(OS, Target, RegBank);
1334 runMCDesc(OS, Target, RegBank);
1335 runTargetHeader(OS, Target, RegBank);
1336 runTargetDesc(OS, Target, RegBank);
1341 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1342 RegisterInfoEmitter(RK).run(OS);
