Lines Matching refs:info
104 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
108 for (n = 0, i = 0; i < info->numInputs; ++i) {
109 switch (info->in[i].sn) {
112 info->in[i].mask = 0x1;
113 info->in[i].slot[0] =
114 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
120 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
128 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
130 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
134 for (i = 0; i < info->numInputs; ++i) {
135 offset = nvc0_shader_input_address(info->in[i].sn,
136 info->in[i].si, ubase);
137 if (info->in[i].patch && offset >= 0x20)
138 offset = 0x20 + info->in[i].si * 0x10;
140 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
141 info->in[i].mask &= 3;
144 info->in[i].slot[c] = (offset + c * 0x4) / 4;
146 nvc0_mesa_varying_hack(&info->in[i]);
153 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
155 unsigned count = info->prop.fp.numColourResults * 4;
158 for (i = 0; i < info->numOutputs; ++i)
159 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
161 info->out[i].slot[c] = info->out[i].si * 4 + c;
163 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
164 info->out[info->io.sampleMask].slot[0] = count++;
166 if (info->target >= 0xe0)
169 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
170 info->out[info->io.fragDepth].slot[2] = count;
176 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
178 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
182 for (i = 0; i < info->numOutputs; ++i) {
183 offset = nvc0_shader_output_address(info->out[i].sn,
184 info->out[i].si, ubase);
185 if (info->out[i].patch && offset >= 0x20)
186 offset = 0x20 + info->out[i].si * 0x10;
189 info->out[i].slot[c] = (offset + c * 0x4) / 4;
191 nvc0_mesa_varying_hack(&info->out[i]);
198 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
202 if (info->type == PIPE_SHADER_VERTEX)
203 ret = nvc0_vp_assign_input_slots(info);
205 ret = nvc0_sp_assign_input_slots(info);
209 if (info->type == PIPE_SHADER_FRAGMENT)
210 ret = nvc0_fp_assign_output_slots(info);
212 ret = nvc0_sp_assign_output_slots(info);
230 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
234 for (i = 0; i < info->numInputs; ++i) {
235 if (info->in[i].patch)
238 a = info->in[i].slot[c];
239 if (info->in[i].mask & (1 << c)) {
240 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
243 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
248 for (i = 0; i < info->numOutputs; ++i) {
249 if (info->out[i].patch)
252 if (!(info->out[i].mask & (1 << c)))
254 assert(info->out[i].slot[c] >= 0x40 / 4);
255 a = info->out[i].slot[c] - 0x40 / 4;
257 if (info->out[i].oread)
258 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
262 for (i = 0; i < info->numSysVals; ++i) {
263 switch (info->sv[i].sn) {
278 vp->vp.clip_enable = info->io.clipDistanceMask;
280 if (info->io.cullDistanceMask & (1 << i))
283 if (info->io.genUserClip < 0)
290 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
295 vp->hdr[18] = info->io.clipDistanceMask;
297 return nvc0_vtgp_gen_header(vp, info);
302 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
304 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
308 switch (info->prop.tp.domain) {
314 if (info->prop.tp.winding > 0)
324 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
327 switch (info->prop.tp.partitioning) {
347 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
351 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
353 if (info->numPatchConstants)
354 opcs = 8 + info->numPatchConstants * 4;
359 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
363 nvc0_vtgp_gen_header(tcp, info);
365 nvc0_tp_get_tess_mode(tcp, info);
373 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
380 nvc0_vtgp_gen_header(tep, info);
382 nvc0_tp_get_tess_mode(tep, info);
391 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
395 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
397 switch (info->prop.gp.outputPrim) {
415 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
417 return nvc0_vtgp_gen_header(gp, info);
436 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
444 if (info->prop.fp.usesDiscard)
446 if (info->prop.fp.numColourResults > 1)
448 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
450 if (info->prop.fp.writesDepth) {
455 for (i = 0; i < info->numInputs; ++i) {
456 m = nvc0_hdr_interp_mode(&info->in[i]);
458 if (!(info->in[i].mask & (1 << c)))
460 a = info->in[i].slot[c];
461 if (info->in[i].slot[0] >= (0x060 / 4) &&
462 info->in[i].slot[0] <= (0x07c / 4)) {
465 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
466 info->in[i].slot[0] <= (0x2fc / 4)) {
469 if (info->in[i].slot[c] < (0x040 / 4) ||
470 info->in[i].slot[c] > (0x380 / 4))
473 if (info->in[i].slot[0] >= (0x300 / 4))
480 for (i = 0; i < info->numOutputs; ++i) {
481 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
482 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
485 fp->fp.early_z = info->prop.fp.earlyFragTests;
491 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
513 info->out[pso->output[i].register_index].slot[s + c];
547 struct nv50_ir_prog_info *info;
550 info = CALLOC_STRUCT(nv50_ir_prog_info);
551 if (!info)
554 info->type = prog->type;
555 info->target = chipset;
556 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
557 info->bin.source = (void *)prog->pipe.tokens;
559 info->io.genUserClip = prog->vp.num_ucps;
560 info
561 info->io.ucpBinding = 15;
563 info->assignSlots = nvc0_program_assign_varying_slots;
566 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
567 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
569 info->optLevel = 3;
572 ret = nv50_ir_generate_code(info);
577 if (info->bin.syms) /* we don't need them yet */
578 FREE(info->bin.syms);
580 prog->code = info->bin.code;
581 prog->code_size = info->bin.codeSize;
582 prog->immd_data = info->immd.buf;
583 prog->immd_size = info->immd.bufSize;
584 prog->relocs = info->bin.relocData;
585 prog->max_gpr = MAX2(4, (info->bin.maxGPR + 1));
587 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
589 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
590 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
591 prog->vp.edgeflag = info->io.edgeFlagIn;
595 ret = nvc0_vp_gen_header(prog, info);
599 ret = nvc0_tcp_gen_header(prog, info);
604 ret = nvc0_tep_gen_header(prog, info);
608 ret = nvc0_gp_gen_header(prog, info);
611 ret = nvc0_fp_gen_header(prog, info);
621 if (info->bin.tlsSpace) {
622 assert(info->bin.tlsSpace < (1 << 24));
624 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
631 if ((info->maxCFDepth * 2) > 16) {
632 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
636 if (info->io.globalAccess)
640 prog->tfb = nvc0_program_create_tfb_state(info,
644 FREE(info);
