Lines Matching refs:CTR
2 {0x00, CTR(0) | CTR(1), 0, "IFU_IFETCH_MISS",
4 {0x01, CTR(0) | CTR(1), 0, "CYCLES_IFU_MEM_STALL",
6 {0x02, CTR(0) | CTR(1), 0, "CYCLES_DATA_STALL",
8 {0x03, CTR(0) | CTR(1), 0, "ITLB_MISS",
10 {0x04, CTR(0) | CTR(1), 0, "DTLB_MISS",
12 {0x05, CTR(0) | CTR(1), 0, "BR_INST_EXECUTED",
14 {0x06, CTR(0) | CTR(1), 0, "BR_INST_MISS_PRED",
16 {0x07, CTR(0) | CTR(1), 0, "INSN_EXECUTED",
18 {0x09, CTR(0) | CTR(1), 0, "DCACHE_ACCESS",
20 {0x0a, CTR(0) | CTR(1), 0, "DCACHE_ACCESS_ALL",
22 {0x0b, CTR(0) | CTR(1), 0, "DCACHE_MISS",
24 {0x0c, CTR(0) | CTR(1), 0, "DCACHE_WB",
26 {0x0d, CTR(0) | CTR(1), 0, "PC_CHANGE",
28 {0x0f, CTR(0) | CTR(1), 0, "TLB_MISS",
30 {0x10, CTR(0) | CTR(1), 0, "EXP_EXTERNAL",
32 {0x11, CTR(0) | CTR(1), 0, "LSU_STALL",
34 {0x12, CTR(0) | CTR(1), 0, "WRITE_DRAIN",
36 {0x20, CTR(0) | CTR(1), 0, "ETMEXTOUT0",
38 {0x21, CTR(0) | CTR(1), 0, "ETMEXTOUT1",
40 {0x22, CTR(0) | CTR(1), 0, "ETMEXTOUT_BOTH",
42 {0xff, CTR(0) | CTR(1) | CTR(2), 0, "CPU_CYCLES",
