Lines Matching refs:HIT
45 0x02 other_core_l2_hitm Counts number of memory load instructions retired where the memory reference hit modified data in a sibling core residing on the same socket
46 0x08 remote_cache_local_home_hit Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and HIT in a remote socket's cache
81 0x01 ld_hit Counts number of loads that hit the L2 cache
84 0x04 rfo_hit Counts the number of store RFO requests that hit the L2 cache
87 0x10 ifetch_hit Counts number of instruction fetches that hit the L2 cache
112 0x0E hit Counts number of L2 store RFO requests where the cache line to be loaded is in either the S, E or M states
118 0xE0 hit Counts number of L2 demand lock RFO requests where the cache line to be loaded is in either the S, E, or M state
145 0x01 hit Counts retired load locks that hit in the L1 data cache or hit in an already allocated fill buffer
146 0x02 s_state Counts L1 data cache retired load locks that hit the target cache line in the shared state
147 0x04 e_state Counts L1 data cache retired load locks that hit the target cache line in the exclusive state
148 0x08 m_state Counts L1 data cache retired load locks that hit the target cache line in the modified state
157 0x10 stlb_hit Counts the number of DTLB first level misses that hit in the second level TLB
186 0x01 hits Counts all instruction fetches that hit the L1 instruction cache
194 0x01 hit Counts number of large ITLB hits
200 0x10 stlb_hit Counts the number of ITLB misses that hit in the second level TLB
264 0x01 hit Counts HIT snoop response sent by this thread in response to a snoop request
265 0x02 hite Counts HIT E snoop response sent by this thread in response to a snoop request
266 0x04 hitm Counts HIT M snoop response sent by this thread in response to a snoop request
297 0x01 l1d_hit Counts number of retired loads that hit the L1 data cache
298 0x02 l2_hit Counts number of retired loads that hit the L2 data cache
299 0x04 llc_unshared_hit Counts number of retired loads that hit their own, unshared lines in the LLC cache
300 0x08 other_core_l2_hit_hitm Counts number of retired loads that hit in a sibling core's L2 (on die core)
322 0x02 bad_target Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the direction was wrong
347 0x01 hit Count L2 HW prefetcher detector hits
354 0x01 promotion Counts the number of L2 secondary misses that hit the Super Queue
