Lines Matching full:x02
5 0x02 branch not-taken mispredicted
16 0x02 ITLB miss
23 0x02 any split stores completed
26 name:load_port_replay type:mandatory default:0x02
27 0x02 split load
28 name:store_port_replay type:mandatory default:0x02
29 0x02 split store
31 0x02 replay cause: unknown store address
37 0x02 read 2nd level cache hit exclusive
47 0x02 bus request type bit 1
63 0x02 rte bit 1: 00=read, 01=read invalidate, 10=write, 11=writeback
77 0x02 handle FP stack overflow
91 0x02 count uops written to queue from TC deliver mode
95 0x02 count non-bogus instructions which are tagged
100 0x02 count marked uops which are bogus
101 name:uop_type type:bitmask default:0x02
102 0x02 count uops which are load operations
106 0x02 count conditional jumps
115 0x02 page walk for instruction TLB miss
118 0x02 count when this processor reads data from bus
