Lines Matching full:x02
10 name:x02 type:mandatory default:0x02
11 0x02 No unit mask
20 0x02 mul Multiply operations executed
23 0x02 bad_target BACLEAR asserted with bad target address
26 0x02 late Late Branch Prediction Unit clears
29 0x02 direct Unconditional branches executed
40 0x02 near_call Retired near call instructions (Precise Event)
44 0x02 direct Mispredicted unconditional branches executed
55 0x02 near_call Mispredicted near retired calls (Precise Event)
59 0x02 l1d Cycles L1D locked
65 0x02 walk_completed DTLB load miss page walks complete
72 0x02 walk_completed DTLB miss page walks
79 0x02 output X87 Floating point assists for invalid output value (Precise Event)
83 0x02 mmx MMX Uops
92 0x02 to_mmx Transitions from Floating Point to MMX instructions
96 0x02 mru Stall cycles due to BPU MRU bypass
102 0x02 x87 Retired floating-point operations (Precise Event)
106 0x02 walk_completed ITLB miss page walks
111 0x02 m_repl L1D cache lines allocated in the M state
116 0x02 miss L1D hardware prefetch misses
120 0x02 s_state L1 writebacks to L2 in S state
126 0x02 misses L1I instruction fetch misses
131 0x02 demand_s_state L2 data demand loads in S state
142 0x02 s_state L2 lines allocated in the S state
147 0x02 demand_dirty L2 modified lines evicted by a demand request
153 0x02 ld_miss L2 load misses
168 0x02 rfo L2 RFO transactions
177 0x02 rfo_s_state L2 demand store RFOs in S state
189 0x02 rs_delayed Loads dispatched from stage 305
194 0x02 reference Longest latency cache reference
197 0x02 mem_order Execution pipeline restart due to Memory ordering conflicts
201 0x02 stores Instructions retired which contains a store (Precise Event)
205 0x02 l2_hit Retired loads that hit the L2 cache (Precise Event)
211 name:mem_uncore_retired type:bitmask default:0x02
212 0x02 local_hitm Load instructions retired that HIT modified data in sibling core (Precise Event)
219 0x02 demand_read_code Offcore demand code read requests
227 0x02 demand_read_code Outstanding offcore demand code reads
232 0x02 registers Partial register stall cycles
238 0x02 load Load buffer stall cycles
247 0x02 packed_shift 128 bit SIMD integer shift operations
255 0x02 packed_shift SIMD integer 64 bit shift operations
263 0x02 invalidate Snoop invalidate requests
267 0x02 invalidate Outstanding snoop invalidate requests
271 0x02 hite Thread responded HITE to snoop
278 0x02 scalar_single SIMD Scalar-Single Uops retired (Precise Event)
287 0x02 ms_cycles_active Uops decoded by Microcode Sequencer
292 0x02 port1 Uops executed on port 1
303 0x02 fused Fused Uops issued
306 0x02 retire_slots Retirement slots used (Precise Event)
