Lines Matching defs:cpu_env
90 static TCGv_ptr cpu_env;
117 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
144 tcg_gen_ld_i32(tmp, cpu_env, offset);
152 tcg_gen_st_i32(var, cpu_env, offset);
378 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
392 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
393 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
580 cpu_env, offsetof(CPUState, GE));
586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
735 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
912 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
914 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
928 gen_helper_vfp_muld(cpu_F1d, cpu_F0d, cpu_F1d, cpu_env);
930 gen_helper_vfp_muls(cpu_F1s, cpu_F0s, cpu_F1s, cpu_env);
963 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
965 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
971 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
973 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
979 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
981 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
1002 tcg_gen_addi_ptr(statusptr, cpu_env, offset); \
1025 tcg_gen_addi_ptr(statusptr, cpu_env, offset); \
1051 tcg_gen_addi_ptr(statusptr, cpu_env, offset); \
1113 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1119 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1125 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1130 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1141 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1143 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1149 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1151 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1157 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1159 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1166 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1171 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1177 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1183 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
2464 gen_helper_get_cp(tmp, cpu_env, tmp2);
2473 gen_helper_set_cp(cpu_env, tmp2, tmp);
2615 gen_helper_get_cp15(tmp, cpu_env, tmp2);
2623 gen_helper_set_cp15(cpu_env, tmp2, tmp);
2878 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2915 gen_helper_vfp_set_fpscr(cpu_env, tmp);
3149 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3157 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3164 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3176 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3200 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3202 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3661 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3667 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3910 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3911 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3913 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
3914 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
3922 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3923 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
4812 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
4814 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
5163 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
5175 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
5780 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5781 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5782 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5783 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5786 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5787 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5788 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5791 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5806 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5807 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5809 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5810 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5813 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5814 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5816 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5817 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5825 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5974 gen_helper_recpe_u32(tmp, tmp, cpu_env);
5977 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
5980 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5983 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
6004 tcg_gen_st_f32(cpu_F0s, cpu_env,
6177 gen_helper_set_teecr(cpu_env, tmp);
6521 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6550 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7322 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7976 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7994 gen_helper_set_r13_banked(cpu_env, tmp, addr);
8193 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
8428 gen_helper_v7m_msr(cpu_env, addr, tmp);
8507 gen_helper_v7m_mrs(tmp, cpu_env, addr);
9425 gen_helper_v7m_msr(cpu_env, addr, tmp);
9431 gen_helper_v7m_msr(cpu_env, addr, tmp);
