Lines Matching full:immediate
708 static Instr EncodeMovwImmediate(uint32_t immediate) {
709 ASSERT(immediate < 0x10000);
710 return ((immediate & 0xf000) << 4) | (immediate & 0xfff);
732 // immediate fits, change the opcode.
775 // if they can be encoded in the ARM's 12 bits of immediate-offset instruction
798 // The immediate operand cannot be encoded as a shifter operand, or use of
819 // No use of constant pool and the immediate operand can be encoded as a
833 // Immediate.
838 // The immediate operand cannot be encoded as a shifter operand, so load
870 // Immediate shift.
889 // Immediate offset.
896 // Immediate offset cannot be encoded, load it first to register ip
922 // Immediate offset.
929 // Immediate offset cannot be encoded, load it first to register ip
1167 void Assembler::movw(Register reg, uint32_t immediate, Condition cond) {
1168 ASSERT(immediate < 0x10000);
1169 mov(reg, Operand(immediate), LeaveCC, cond);
1173 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) {
1174 emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate));
1379 // Immediate.
1384 // Immediate operand cannot be encoded, load it first to register ip.
1916 // VMOV can accept an immediate of the form:
1920 // The immediate is encoded using an 8-bit quantity, comprised of two
1921 // 4-bit fields. For an 8-bit immediate of the form:
1925 // where a is the MSB and h is the LSB, an immediate 64-bit double can be
1952 // Create the encoded immediate in the form:
1965 // Dd = immediate
