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Lines Matching refs:n3

315 void log_3I(InstrInfo* n, InstrInfo* n2, InstrInfo* n3)
319    n3->parent->Ir.a++;
348 void log_3I_0D_cache_access(InstrInfo* n, InstrInfo* n2, InstrInfo* n3)
355    //            n3, n3->instr_addr, n3->instr_len);
362    cachesim_I1_doref(n3->instr_addr, n3->instr_len, 
363                      &n3->parent->Ir.m1, &n3->parent->Ir.mL);
364    n3->parent->Ir.a++;