Lines Matching refs:dRow0
50 VLD1 dRow0, [pSrc], srcStep
59 VST1 dRow0, [pDst@64], dstStep
97 VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep
98 VEXT dRow0Shft, dRow0, dRow0Shft, #1
113 $M_VHADDR dRow0, dRow0, dRow0Shft
115 VST1 dRow0, [pDst@64], dstStep
158 VLD1 dRow0, [pSrc], srcStep
166 $M_VHADDR dRow0, dRow0, dRow1
169 VST1 dRow0, [pDst@64], dstStep
191 ;// 1. VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep ;// Load the row and next 8 bytes
192 ;// 2. VEXT dRow0Shft, dRow0, dRow0Shft, #1 ;// Generate the shifted row
193 ;// 3. VADDL qSum0, dRow0, dRow0Shft ;// Generate the sum of row and shifted row
195 ;// 6. VSHRN dRow0, qSum0, #2 ;// Divide by 4
196 ;// 7. VST1 dRow0, [pDst@64], dstStep ;// Store
219 VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep
222 VEXT dRow0Shft, dRow0, dRow0Shft, #1
228 VADDL qSum0, dRow0, dRow0Shft
243 VSHRN dRow0, qSum0, #2
248 VST1 dRow0, [pDst@64], dstStep
293 dRow0 DN D0.U8
