Lines Matching full:rot64
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offset_8 endian_t2h_16 endian_h2t_16 swap_16 endian_h2be_16 endian_be2h_16 endian_h2le_16 endian_le2h_16 offset_16 sim_endian_split_16 sim_endian_join_16 sim_core_find_mapping sim_core_translate sim_core_dummy_16 sim_core_trace_16 sim_core_read_aligned_16 sim_core_read_unaligned_16 sim_core_write_aligned_16 sim_core_write_unaligned_16 sim_core_dummy_8 sim_core_trace_8 sim_core_read_aligned_8 sim_core_read_unaligned_8 sim_core_write_aligned_8 sim_core_write_unaligned_8 sim_core_read_misaligned_7 sim_core_write_misaligned_7 sim_core_read_misaligned_6 sim_core_write_misaligned_6 sim_core_read_misaligned_5 sim_core_write_misaligned_5 sim_core_dummy_4 sim_core_trace_4 sim_core_read_aligned_4 sim_core_read_unaligned_4 sim_core_write_aligned_4 sim_core_write_unaligned_4 sim_core_read_misaligned_3 sim_core_write_misaligned_3 sim_core_dummy_2 sim_core_trace_2 sim_core_read_aligned_2 sim_core_read_unaligned_2 sim_core_write_aligned_2 sim_core_write_unaligned_2 sim_core_trace_1 sim_core_read_aligned_1 sim_core_write_aligned_1 sim_events_poll sim_events_free sim_events_time sim_events_elapsed_time sim_events_remain_time update_time_from_event sim_watch_valid sim_events_tick sim_events_tickn sim_events_slip sim_events_preprocess sim_events_process print_bits pack_fpu unpack_fpu fpu2i sim_fpu_is_zero sim_fpu_is_snan sim_fpu_is_qnan sim_fpu_is_infinity i2fpu fpu2u sim_fpu_is_nan u2fpu sim_fpu_32to sim_fpu_232to sim_fpu_64to sim_fpu_to32 sim_fpu_to232 sim_fpu_to64 sim_fpu_fractionto sim_fpu_tofraction do_normal_overflow do_normal_underflow do_normal_round do_round sim_fpu_round_32 sim_fpu_round_64 sim_fpu_add sim_fpu_sub sim_fpu_mul sim_fpu_div sim_fpu_max sim_fpu_min sim_fpu_neg sim_fpu_abs sim_fpu_inv sim_fpu_sqrt sim_fpu_i32to sim_fpu_u32to sim_fpu_i64to sim_fpu_u64to sim_fpu_to32i sim_fpu_to32u sim_fpu_to64i sim_fpu_to64u sim_fpu_2d sim_fpu_d2 sim_fpu_is_number sim_fpu_is_denorm sim_fpu_sign sim_fpu_exp sim_fpu_fraction sim_fpu_guard sim_fpu_is sim_fpu_cmp sim_fpu_is_lt sim_fpu_lt sim_fpu_is_le sim_fpu_le sim_fpu_is_eq sim_fpu_eq sim_fpu_is_ne sim_fpu_ne sim_fpu_is_ge sim_fpu_ge sim_fpu_is_gt sim_fpu_gt sim_fpu_print_fpu sim_fpu_printn_fpu sim_fpu_print_status address_translation prefetch load_memory store_memory ifetch32 ifetch16 sync_operation cache_op icache_warning.10745 dcache_warning.10746 pending_tick semantic_illegal delayslot32 nullify_next_insn32 loadstore_ea not_word_value unpredictable check_mf_cycles check_mt_hilo check_mf_hilo check_mult_hilo check_div_hilo check_u64 do_addiu do_addu do_and do_daddiu do_daddu do_ddiv do_ddivu do_div do_divu do_dmultx do_dmult do_dmultu do_dror do_dsll do_dsllv do_dsra do_dsrav do_dsrl do_dsrlv do_dsubu do_load do_load_left do_load_right do_mfhi do_mflo do_mult do_multu do_nor do_or do_ori do_ror do_store do_store_left do_store_right do_sll do_sllv do_slt do_slti do_sltiu do_sltu do_sra do_srav do_srl do_srlv do_subu do_xor do_xori str_FMT str_TF str_ND str_COND check_fmt_p check_fpu delayslot16 basepc do_save str_MFHI str_SAT str_UNS do_vr_mul_op do_ph_op do_w_op do_qb_op do_qb_shift do_ph_shift do_w_shll do_w_shra do_qb_muleu do_ph_mulq do_ph_muleq do_qb_dot_product do_ph_dot_product do_w_dot_product do_ph_maq do_qb_cmpu do_qb_cmpgu do_ph_cmpu do_w_extr do_h_extr do_extp do_shilo do_u_ph_op do_uh_qb_op do_qb_cmpgdu do_w_ph_dot_product do_w_mulq do_precr_sra do_qb_shra do_ph_shrl do_qh_ph_op do_qh_w_op do_x_w_ph_dot_product do_qx_w_ph_dot_product sim_io_error current_target_byte_order mips_core_signal trace_printf map_to_str sim_core_xor_read_buffer sim_core_xor_write_buffer sim_events_schedule sim_io_poll_quit free sim_elapsed_time_since sim_core_read_buffer abort sim_fpu_qnan sim_fpu_zero sim_fpu_one pr_addr signal_exception sim_io_eprintf sim_engine_abort idecode_issue tracefh dotrace itable trace_input_word2 trace_result_word1 __divdi3 __moddi3 trace_result_word2 __udivdi3 __umoddi3 trace_input_word1 DSPLO_REGNUM DSPHI_REGNUM semantic_RSVD_SPECIAL trace_prefix trace_generic semantic_SYSCALL_SPECIAL semantic_BREAK_SPECIAL sim_engine_halt semantic_TGE_SPECIAL semantic_TGEU_SPECIAL semantic_TLT_SPECIAL semantic_TLTU_SPECIAL semantic_TEQ_SPECIAL semantic_TNE_SPECIAL semantic_SLLV_SPECIAL semantic_SRLV_SPECIAL semantic_SRAV_SPECIAL semantic_MOVZ_SPECIAL semantic_MOVN_SPECIAL semantic_ADD_SPECIAL semantic_ADDU_SPECIAL semantic_SUB_SPECIAL semantic_SUBU_SPECIAL semantic_AND_SPECIAL semantic_OR_SPECIAL semantic_XOR_SPECIAL semantic_NOR_SPECIAL semantic_SLT_SPECIAL semantic_SLTU_SPECIAL semantic_MULT_SPECIAL semantic_MULTU_SPECIAL semantic_DIV_SPECIAL semantic_DIVU_SPECIAL semantic_MOVtf_SPECIAL semantic_JALR_SPECIAL semantic_JR_SPECIAL semantic_MTHI_SPECIAL semantic_MTLO_SPECIAL semantic_SLLa_SPECIAL semantic_SRL_SPECIAL semantic_SRA_SPECIAL semantic_MFHI_SPECIAL semantic_MFLO_SPECIAL semantic_SYNC_SPECIAL semantic_BLTZ_REGIMM semantic_BGEZ_REGIMM semantic_BLTZL_REGIMM semantic_BGEZL_REGIMM semantic_TGEI_REGIMM semantic_TGEIU_REGIMM semantic_TLTI_REGIMM semantic_TLTIU_REGIMM semantic_TEQI_REGIMM semantic_TNEI_REGIMM semantic_BLTZAL_REGIMM semantic_BGEZAL_REGIMM semantic_BLTZALL_REGIMM semantic_BGEZALL_REGIMM semantic_J_NORMAL semantic_JAL_NORMAL semantic_BEQ_NORMAL semantic_BNE_NORMAL semantic_BLEZ_NORMAL semantic_BGTZ_NORMAL semantic_ADDI_NORMAL semantic_ADDIU_NORMAL semantic_SLTI_NORMAL semantic_SLTIU_NORMAL semantic_ANDI_NORMAL semantic_ORI_NORMAL semantic_XORI_NORMAL semantic_LUI_NORMAL semantic_COPz_NORMAL decode_coproc semantic_MFC0_COP0 trace_input0 semantic_MTC0_COP0 semantic_BC0F_COP0 semantic_BC0T_COP0 semantic_BC0FL_COP0 semantic_BC0TL_COP0 semantic_TLBR_COP0 semantic_TLBWI_COP0 semantic_TLBWR_COP0 semantic_TLBP_COP0 semantic_RFE_COP0 semantic_ERET_COP0 sim_io_printf semantic_MFC1b_COP1 semantic_CFC1b_COP1 value_fcr semantic_MTC1b_COP1 store_fpr semantic_CTC1b_COP1 store_fcr semantic_BC1b_COP1S semantic_ADD_fmt_COP1 value_fpr fp_add semantic_SUB_fmt_COP1 fp_sub semantic_MUL_fmt_COP1 fp_mul semantic_DIV_fmt_COP1 fp_div semantic_MOVZ_fmt_COP1 semantic_MOVN_fmt_COP1 semantic_C_cond_fmtb_COP1 fp_cmp semantic_MOVtf_fmt_COP1 ps_lower ps_upper pack_ps semantic_SQRT_fmt_COP1 fp_sqrt semantic_ABS_fmt_COP1 fp_abs semantic_MOV_fmt_COP1 semantic_NEG_fmt_COP1 fp_neg semantic_ROUND_L_fmt_COP1 convert semantic_TRUNC_L_fmt_COP1 semantic_CEIL_L_fmt_COP1 semantic_FLOOR_L_fmt_COP1 semantic_ROUND_W_fmt_COP1 semantic_TRUNC_W_COP1 semantic_CEIL_W_COP1 semantic_FLOOR_W_fmt_COP1 semantic_RECIP_fmt_COP1 fp_recip semantic_RSQRT_fmt_COP1 fp_rsqrt semantic_CVT_S_fmt_COP1 semantic_CVT_D_fmt_COP1 semantic_CVT_W_fmt_COP1 semantic_CVT_L_fmt_COP1 semantic_MADD_fmt_COP1X fp_madd semantic_MSUB_fmt_COP1X fp_msub semantic_NMADD_fmt_COP1X fp_nmadd semantic_NMSUB_fmt_COP1X fp_nmsub semantic_SWXC1_COP1X cop_sw semantic_PREFX_COP1X semantic_LWXC1_COP1X cop_lw semantic_BEQL_NORMAL semantic_BNEL_NORMAL semantic_BLEZL_NORMAL semantic_BGTZL_NORMAL semantic_LB_NORMAL semantic_LH_NORMAL semantic_LWL_NORMAL semantic_LW_NORMAL semantic_LBU_NORMAL semantic_LHU_NORMAL semantic_LWR_NORMAL semantic_SB_NORMAL semantic_SH_NORMAL semantic_SWL_NORMAL semantic_SW_NORMAL semantic_SWR_NORMAL semantic_CACHE_NORMAL semantic_LWCz_NORMAL semantic_LL_NORMAL semantic_LWC1_COP1 semantic_PREF_NORMAL semantic_LDC1b_COP1 cop_ld semantic_SWCz_NORMAL semantic_SC_NORMAL semantic_SWC1_COP1 semantic_SDC1b_COP1 cop_sd ? % Q P ? ? ? Q < w ? ? Q B } ? ? Q B Y e Q ? ? ? ? Q L ? ? ? Q ? 5 L X Q ? ? ? Q X ? ? ? Q Z q } Q ?
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B X k ~ ? ? ? ? ? ? idecode.c LSMASKED MSMASKED LSEXTRACTED MSEXTRACTED LSINSERTED MSINSERTED LSSEXT LSSEXT32 MSSEXT MSSEXT32 LSMASKED8 MSMASKED8 LSEXTRACTED8 MSEXTRACTED8 LSINSERTED8 MSINSERTED8 ROT8 ROTR8 ROTL8 LSSEXT8 MSSEXT8 LSMASKED16 MSMASKED16 LSEXTRACTED16 MSEXTRACTED16 LSINSERTED16 MSINSERTED16 ROT16 ROTR16 ROTL16 LSSEXT16 MSSEXT16 LSMASKED32 MSMASKED32 LSEXTRACTED32 MSEXTRACTED32 LSINSERTED32 MSINSERTED32 ROT32 ROTR32 ROTL32 LSMASKED64 MSMASKED64 LSEXTRACTED64 MSEXTRACTED64 LSINSERTED64 MSINSERTED64 ROT64 ROTR64 ROTL64 LSSEXT64 MSSEXT64 endian_t2h_1 endian_h2t_1 swap_1 endian_h2be_1 endian_be2h_1 endian_h2le_1 endian_le2h_1 offset_1 endian_t2h_2 endian_h2t_2 swap_2 endian_h2be_2 endian_be2h_2 endian_h2le_2 endian_le2h_2 offset_2 endian_t2h_4 endian_h2t_4 swap_4 endian_h2be_4 endian_be2h_4 endian_h2le_4 endian_le2h_4 offset_4 endian_t2h_8 endian_h2t_8 swap_8 endian_h2be_8 endian_be2h_8 endian_h2le_8 endian_le2h_8 offset_8 endian_t2h_16 endian_h2t_16 swap_16 endian_h2be_16 endian_be2h_16 endian_h2le_16 endian_le2h_16 offset_16 sim_endian_split_16 sim_endian_join_16 sim_core_find_mapping sim_core_translate sim_core_dummy_16 sim_core_trace_16 sim_core_read_aligned_16 sim_core_read_unaligned_16 sim_core_write_aligned_16 sim_core_write_unaligned_16 sim_core_dummy_8 sim_core_trace_8 sim_core_read_aligned_8 sim_core_read_unaligned_8 sim_core_write_aligned_8 sim_core_write_unaligned_8 sim_core_read_misaligned_7 sim_core_write_misaligned_7 sim_core_read_misaligned_6 sim_core_write_misaligned_6 sim_core_read_misaligned_5 sim_core_write_misaligned_5 sim_core_dummy_4 sim_core_trace_4 sim_core_read_aligned_4 sim_core_read_unaligned_4 sim_core_write_aligned_4 sim_core_write_unaligned_4 sim_core_read_misaligned_3 sim_core_write_misaligned_3 sim_core_dummy_2 sim_core_trace_2 sim_core_read_aligned_2 sim_core_read_unaligned_2 sim_core_write_aligned_2 sim_core_write_unaligned_2 sim_core_trace_1 sim_core_read_aligned_1 sim_core_write_aligned_1 sim_events_poll sim_events_free sim_events_time sim_events_elapsed_time sim_events_remain_time update_time_from_event sim_watch_valid sim_events_tick sim_events_tickn sim_events_slip sim_events_preprocess sim_events_process print_bits pack_fpu unpack_fpu fpu2i sim_fpu_is_zero sim_fpu_is_snan sim_fpu_is_qnan sim_fpu_is_infinity i2fpu fpu2u sim_fpu_is_nan u2fpu sim_fpu_32to sim_fpu_232to sim_fpu_64to sim_fpu_to32 sim_fpu_to232 sim_fpu_to64 sim_fpu_fractionto sim_fpu_tofraction do_normal_overflow do_normal_underflow do_normal_round do_round sim_fpu_round_32 sim_fpu_round_64 sim_fpu_add sim_fpu_sub sim_fpu_mul sim_fpu_div sim_fpu_max sim_fpu_min sim_fpu_neg sim_fpu_abs sim_fpu_inv sim_fpu_sqrt sim_fpu_i32to sim_fpu_u32to sim_fpu_i64to sim_fpu_u64to sim_fpu_to32i sim_fpu_to32u sim_fpu_to64i sim_fpu_to64u sim_fpu_2d sim_fpu_d2 sim_fpu_is_number sim_fpu_is_denorm sim_fpu_sign sim_fpu_exp sim_fpu_fraction sim_fpu_guard sim_fpu_is sim_fpu_cmp sim_fpu_is_lt sim_fpu_lt sim_fpu_is_le sim_fpu_le sim_fpu_is_eq sim_fpu_eq sim_fpu_is_ne sim_fpu_ne sim_fpu_is_ge sim_fpu_ge sim_fpu_is_gt sim_fpu_gt sim_fpu_print_fpu sim_fpu_printn_fpu sim_fpu_print_status address_translation prefetch load_memory store_memory ifetch32 ifetch16 sync_operation cache_op icache_warning.10745 dcache_warning.10746 pending_tick semantic_illegal delayslot32 nullify_next_insn32 loadstore_ea not_word_value unpredictable check_mf_cycles check_mt_hilo check_mf_hilo check_mult_hilo check_div_hilo check_u64 do_addiu do_addu do_and do_daddiu do_daddu do_ddiv do_ddivu do_div do_divu do_dmultx do_dmult do_dmultu do_dror do_dsll do_dsllv do_dsra do_dsrav do_dsrl do_dsrlv do_dsubu do_load do_load_left do_load_right do_mfhi do_mflo do_mult do_multu do_nor do_or do_ori do_ror do_store do_store_left do_store_right do_sll do_sllv do_slt do_slti do_sltiu do_sltu do_sra do_srav do_srl do_srlv do_subu do_xor do_xori str_FMT str_TF str_ND str_COND check_fmt_p check_fpu delayslot16 basepc do_save str_MFHI str_SAT str_UNS do_vr_mul_op do_ph_op do_w_op do_qb_op do_qb_shift do_ph_shift do_w_shll do_w_shra do_qb_muleu do_ph_mulq do_ph_muleq do_qb_dot_product do_ph_dot_product do_w_dot_product do_ph_maq do_qb_cmpu do_qb_cmpgu do_ph_cmpu do_w_extr do_h_extr do_extp do_shilo do_u_ph_op do_uh_qb_op do_qb_cmpgdu do_w_ph_dot_product do_w_mulq do_precr_sra do_qb_shra do_ph_shrl do_qh_ph_op do_qh_w_op do_x_w_ph_dot_product do_qx_w_ph_dot_product sim_io_error current_target_byte_order mips_core_signal trace_printf map_to_str sim_core_xor_read_buffer sim_core_xor_write_buffer sim_events_schedule sim_io_poll_quit free sim_elapsed_time_since sim_core_read_buffer abort sim_fpu_qnan sim_fpu_zero sim_fpu_one pr_addr signal_exception sim_io_eprintf sim_engine_abort idecode_issue tracefh dotrace itable trace_input_word2 trace_result_word1 __divdi3 __moddi3 trace_result_word2 __udivdi3 __umoddi3 trace_input_word1 DSPLO_REGNUM DSPHI_REGNUM semantic_SLLa_SPECIAL semantic_MOVtf_SPECIAL semantic_SRL_SPECIAL semantic_SRA_SPECIAL semantic_SLLV_SPECIAL semantic_RSVD_SPECIAL semantic_SRLV_SPECIAL semantic_SRAV_SPECIAL semantic_JR_SPECIAL semantic_JALR_SPECIAL semantic_MOVZ_SPECIAL semantic_MOVN_SPECIAL semantic_SYSCALL_SPECIAL semantic_BREAK_SPECIAL semantic_SYNC_SPECIAL semantic_MFHI_SPECIAL semantic_MTHI_SPECIAL semantic_MFLO_SPECIAL semantic_MTLO_SPECIAL semantic_MULT_SPECIAL semantic_MULTU_SPECIAL semantic_DIV_SPECIAL semantic_DIVU_SPECIAL semantic_ADD_SPECIAL semantic_ADDU_SPECIAL semantic_SUB_SPECIAL semantic_SUBU_SPECIAL semantic_AND_SPECIAL semantic_OR_SPECIAL semantic_XOR_SPECIAL semantic_NOR_SPECIAL semantic_SLT_SPECIAL semantic_SLTU_SPECIAL semantic_TGE_SPECIAL semantic_TGEU_SPECIAL semantic_TLT_SPECIAL semantic_TLTU_SPECIAL semantic_TEQ_SPECIAL semantic_TNE_SPECIAL semantic_BLTZ_REGIMM semantic_BGEZ_REGIMM semantic_BLTZL_REGIMM semantic_BGEZL_REGIMM semantic_TGEI_REGIMM semantic_TGEIU_REGIMM semantic_TLTI_REGIMM semantic_TLTIU_REGIMM semantic_TEQI_REGIMM semantic_TNEI_REGIMM semantic_BLTZAL_REGIMM semantic_BGEZAL_REGIMM semantic_BLTZALL_REGIMM semantic_BGEZALL_REGIMM semantic_J_NORMAL semantic_JAL_NORMAL semantic_BEQ_NORMAL semantic_BNE_NORMAL semantic_BLEZ_NORMAL semantic_BGTZ_NORMAL semantic_ADDI_NORMAL semantic_ADDIU_NORMAL semantic_SLTI_NORMAL semantic_SLTIU_NORMAL semantic_ANDI_NORMAL semantic_ORI_NORMAL semantic_XORI_NORMAL semantic_LUI_NORMAL semantic_MFC0_COP0 semantic_MTC0_COP0 semantic_BC0F_COP0 semantic_BC0T_COP0 semantic_BC0FL_COP0 semantic_BC0TL_COP0 semantic_TLBR_COP0 semantic_TLBWI_COP0 semantic_TLBWR_COP0 semantic_TLBP_COP0 semantic_RFE_COP0 semantic_ERET_COP0 semantic_MFC1b_COP1 semantic_CFC1b_COP1 semantic_MTC1b_COP1 semantic_CTC1b_COP1 semantic_BC1b_COP1S semantic_ADD_fmt_COP1 semantic_SUB_fmt_COP1 semantic_MUL_fmt_COP1 semantic_DIV_fmt_COP1 semantic_SQRT_fmt_COP1 semantic_ABS_fmt_COP1 semantic_MOV_fmt_COP1 semantic_NEG_fmt_COP1 semantic_ROUND_L_fmt_COP1 semantic_TRUNC_L_fmt_COP1 semantic_CEIL_L_fmt_COP1 semantic_FLOOR_L_fmt_COP1 semantic_ROUND_W_fmt_COP1 semantic_TRUNC_W_COP1 semantic_CEIL_W_COP1 semantic_FLOOR_W_fmt_COP1 semantic_MOVtf_fmt_COP1 semantic_MOVZ_fmt_COP1 semantic_MOVN_fmt_COP1 semantic_RECIP_fmt_COP1 semantic_RSQRT_fmt_COP1 semantic_CVT_S_fmt_COP1 semantic_CVT_D_fmt_COP1 semantic_CVT_W_fmt_COP1 semantic_CVT_L_fmt_COP1 semantic_C_cond_fmtb_COP1 semantic_COPz_NORMAL semantic_LWXC1_COP1X semantic_SWXC1_COP1X semantic_PREFX_COP1X semantic_MADD_fmt_COP1X semantic_MSUB_fmt_COP1X semantic_NMADD_fmt_COP1X semantic_NMSUB_fmt_COP1X semantic_BEQL_NORMAL semantic_BNEL_NORMAL semantic_BLEZL_NORMAL semantic_BGTZL_NORMAL semantic_LB_NORMAL semantic_LH_NORMAL semantic_LWL_NORMAL semantic_LW_NORMAL semantic_LBU_NORMAL semantic_LHU_NORMAL semantic_LWR_NORMAL semantic_SB_NORMAL semantic_SH_NORMAL semantic_SWL_NORMAL semantic_SW_NORMAL semantic_SWR_NORMAL semantic_CACHE_NORMAL semantic_LL_NORMAL semantic_LWC1_COP1 semantic_LWCz_NORMAL semantic_PREF_NORMAL semantic_LDC1b_COP1 semantic_SC_NORMAL semantic_SWC1_COP1 semantic_SWCz_NORMAL semantic_SDC1b_COP1 ? % Q P ? ? ? Q < w ? ? Q B } ? ? Q B Y e Q ? ? ? ? Q L ? ? ? Q ? 5 L X Q ? ? ? Q X ? ? ? Q Z q } Q ?
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