Lines Matching refs:Rs
248 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs)
614 int Rd, int Rm, int Rs, int Rn) {
618 mMips->MUL(R_at, Rm, Rs);
627 int Rd, int Rm, int Rs) {
629 mMips->MUL(Rd, Rm, Rs);
637 int RdLo, int RdHi, int Rm, int Rs) {
639 mMips->MULT(Rm, Rs);
650 int RdLo, int RdHi, int Rm, int Rs) {
652 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
654 // (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
666 int RdLo, int RdHi, int Rm, int Rs) {
668 "SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
670 // (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
681 int RdLo, int RdHi, int Rm, int Rs) {
683 "SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
685 // (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
1082 int Rd, int Rm, int Rs)
1088 // where x corresponds to Rm and y to Rs
1103 // select half-reg for Rs
1106 mMips->SRA(R_at2, Rs, 16);
1110 mMips->SEH(R_at2, Rs);
1112 mMips->SLL(R_at2, Rs, 16);
1121 int Rd, int Rm, int Rs)
1125 // the selector yT or yB refers to reg Rs
1128 mMips->SRL(R_at, Rs, 16);
1133 mMips->SLL(R_at, Rs, 16);
1139 // 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
1141 int Rd, int Rm, int Rs, int Rn)
1147 // where x corresponds to Rm and y to Rs
1162 // select half-reg for Rs
1165 mMips->SRA(R_at2, Rs, 16);
1169 mMips->SEH(R_at2, Rs);
1171 mMips->SLL(R_at2, Rs, 16);
1181 int RdHi, int RdLo, int Rs, int Rm)
1183 // *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm;
1190 int Rd, int Rm, int Rs, int Rn)
1192 // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
1439 void MIPSAssembler::ADDU(int Rd, int Rs, int Rt)
1442 | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF);
1445 // MD00086 pdf says this is: ADDIU rt, rs, imm -- they do not use Rd
1446 void MIPSAssembler::ADDIU(int Rt, int Rs, int16_t imm)
1448 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1452 void MIPSAssembler::SUBU(int Rd, int Rs, int Rt)
1455 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ;
1459 void MIPSAssembler::SUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j)
1461 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm) & MSK_16);
1465 void MIPSAssembler::NEGU(int Rd, int Rs) // really subu(d, zero, s)
1467 MIPSAssembler::SUBU(Rd, 0, Rs);
1470 void MIPSAssembler::MUL(int Rd, int Rs, int Rt)
1473 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ;
1476 void MIPSAssembler::MULT(int Rs, int Rt) // dest is hi,lo
1478 *mPC++ = (spec_op<<OP_SHF) | (mult_fn<<FUNC_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF);
1481 void MIPSAssembler::MULTU(int Rs, int Rt) // dest is hi,lo
1483 *mPC++ = (spec_op<<OP_SHF) | (multu_fn<<FUNC_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF);
1486 void MIPSAssembler::MADD(int Rs, int Rt) // hi,lo = hi,lo + Rs * Rt
1488 *mPC++ = (spec2_op<<OP_SHF) | (madd_fn<<FUNC_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF);
1491 void MIPSAssembler::MADDU(int Rs, int Rt) // hi,lo = hi,lo + Rs * Rt
1493 *mPC++ = (spec2_op<<OP_SHF) | (maddu_fn<<FUNC_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF);
1497 void MIPSAssembler::MSUB(int Rs, int Rt) // hi,lo = hi,lo - Rs * Rt
1499 *mPC++ = (spec2_op<<OP_SHF) | (msub_fn<<FUNC_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF);
1502 void MIPSAssembler::MSUBU(int Rs, int Rt) // hi,lo = hi,lo - Rs * Rt
1504 *mPC++ = (spec2_op<<OP_SHF) | (msubu_fn<<FUNC_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF);
1527 void MIPSAssembler::SLT(int Rd, int Rs, int Rt)
1530 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1533 void MIPSAssembler::SLTI(int Rt, int Rs, int16_t imm)
1535 *mPC++ = (slti_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1539 void MIPSAssembler::SLTU(int Rd, int Rs, int Rt)
1542 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1545 void MIPSAssembler::SLTIU(int Rt, int Rs, int16_t imm)
1547 *mPC++ = (sltiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1557 void MIPSAssembler::AND(int Rd, int Rs, int Rt)
1560 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1563 void MIPSAssembler::ANDI(int Rt, int Rs, uint16_t imm) // todo: support larger immediate
1565 *mPC++ = (andi_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1569 void MIPSAssembler::OR(int Rd, int Rs, int Rt)
1572 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1575 void MIPSAssembler::ORI(int Rt, int Rs, uint16_t imm)
1577 *mPC++ = (ori_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1580 void MIPSAssembler::NOR(int Rd, int Rs, int Rt)
1583 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1586 void MIPSAssembler::NOT(int Rd, int Rs)
1588 MIPSAssembler::NOR(Rd, Rs, 0); // NOT(d,s) = NOR(d,s,zero)
1591 void MIPSAssembler::XOR(int Rd, int Rs, int Rt)
1594 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1597 void MIPSAssembler::XORI(int Rt, int Rs, uint16_t imm) // todo: support larger immediate
1599 *mPC++ = (xori_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1608 void MIPSAssembler::SLLV(int Rd, int Rt, int Rs)
1611 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1620 void MIPSAssembler::SRLV(int Rd, int Rt, int Rs)
1623 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1632 void MIPSAssembler::SRAV(int Rd, int Rt, int Rs)
1635 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1645 void MIPSAssembler::ROTRV(int Rd, int Rt, int Rs) // mips32r2
1649 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (1<<RE_SHF);
1653 void MIPSAssembler::RORsyn(int Rd, int Rt, int Rs)
1656 MIPSAssembler::NEGU(R_at2, Rs);
1658 MIPSAssembler::SRLV(Rd, Rt, Rs);
1672 void MIPSAssembler::CLO(int Rd, int Rs)
1676 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rd<<RT_SHF);
1679 void MIPSAssembler::CLZ(int Rd, int Rs)
1683 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rd<<RT_SHF);
1753 void MIPSAssembler::MOVE(int Rd, int Rs)
1755 // encoded as "or rd, rs, zero"
1757 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (0<<RT_SHF);
1760 void MIPSAssembler::MOVN(int Rd, int Rs, int Rt)
1763 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1766 void MIPSAssembler::MOVZ(int Rd, int Rs, int Rt)
1769 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1782 void MIPSAssembler::MTHI(int Rs)
1784 *mPC++ = (spec_op<<OP_SHF) | (mthi_fn<<FUNC_SHF) | (Rs<<RS_SHF);
1787 void MIPSAssembler::MTLO(int Rs)
1789 *mPC++ = (spec_op<<OP_SHF) | (mtlo_fn<<FUNC_SHF) | (Rs<<RS_SHF);
1812 void MIPSAssembler::BEQ(int Rs, int Rt, const char* label)
1815 *mPC++ = (beq_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | 0;
1819 void MIPSAssembler::BNE(int Rs, int Rt, const char* label)
1822 *mPC++ = (bne_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | 0;
1826 void MIPSAssembler::BLEZ(int Rs, const char* label)
1829 *mPC++ = (blez_op<<OP_SHF) | (0<<RT_SHF) | (Rs<<RS_SHF) | 0;
1833 void MIPSAssembler::BLTZ(int Rs, const char* label)
1836 *mPC++ = (regimm_op<<OP_SHF) | (bltz_fn<<RT_SHF) | (Rs<<RS_SHF) | 0;
1840 void MIPSAssembler::BGTZ(int Rs, const char* label)
1843 *mPC++ = (bgtz_op<<OP_SHF) | (0<<RT_SHF) | (Rs<<RS_SHF) | 0;
1848 void MIPSAssembler::BGEZ(int Rs, const char* label)
1851 *mPC++ = (regimm_op<<OP_SHF) | (bgez_fn<<RT_SHF) | (Rs<<RS_SHF) | 0;
1855 void MIPSAssembler::JR(int Rs)
1857 *mPC++ = (spec_op<<OP_SHF) | (Rs<<RS_SHF) | (jr_fn << FUNC_SHF);
1868 void MIPSAssembler::BEQZ(int Rs, const char* label)
1870 BEQ(Rs, R_zero, label);
1873 void MIPSAssembler::BNEZ(int Rs, const char* label)
1878 void MIPSAssembler::BGE(int Rs, int Rt, const char* label)
1880 SLT(R_at, Rs, Rt);
1884 void MIPSAssembler::BGEU(int Rs, int Rt, const char* label)
1886 SLTU(R_at, Rs, Rt);
1890 void MIPSAssembler::BGT(int Rs, int Rt, const char* label)
1892 SLT(R_at, Rt, Rs); // rev
1896 void MIPSAssembler::BGTU(int Rs, int Rt, const char* label)
1898 SLTU(R_at, Rt, Rs); // rev
1902 void MIPSAssembler::BLE(int Rs, int Rt, const char* label)
1904 SLT(R_at, Rt, Rs); // rev
1908 void MIPSAssembler::BLEU(int Rs, int Rt, const char* label)
1910 SLTU(R_at, Rt, Rs); // rev
1914 void MIPSAssembler::BLT(int Rs, int Rt, const char* label)
1916 SLT(R_at, Rs, Rt);
1920 void MIPSAssembler::BLTU(int Rs, int Rt, const char* label)
1922 SLTU(R_at, Rs, Rt);
