| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 146 int64_t Amount = I->getOperand(0).getImm();
149 Amount = -Amount;
154 TII.adjustStackPtr(Mips::SP, Amount, MBB, I);
|
| MipsSEFrameLowering.cpp | 486 int64_t Amount = I->getOperand(0).getImm();
489 Amount = -Amount;
492 TII.adjustStackPtr(SP, Amount, MBB, I);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 238 uint64_t Amount = Old->getOperand(0).getImm();
239 if (Amount != 0) {
241 // amount of space needed for the outgoing arguments up to the next
243 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
249 .addReg(MSP430::SPW).addImm(Amount);
252 // factor out the amount the callee already popped.
254 Amount -= CalleeAmt;
255 if (Amount)
258 .addReg(MSP430::SPW).addImm(Amount);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_emulate_loops.c | 53 float Amount;
119 float amount; local
156 amount = rc_get_constant_value(count_inst->C,
167 count_inst->Amount += amount;
174 count_inst->Amount -= amount;
232 count_inst.Amount = 0.0f;
272 if(count_inst.Amount == 0.0f){
275 DBG("Counter is increased by %f each iteration.\n", count_inst.Amount);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 56 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
57 // ADJCALLSTACKUP -> add, sp, sp, amount
60 unsigned Amount = Old->getOperand(0).getImm();
61 if (Amount != 0) {
63 // amount of space needed for the outgoing arguments up to the next
66 Amount = (Amount+Align-1)/Align*Align;
71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
|
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 313 uint64_t Amount = Old->getOperand(0).getImm();
314 if (Amount != 0) {
316 // amount of space needed for the outgoing arguments up to the next
319 Amount = (Amount+Align-1)/Align*Align;
321 assert(Amount%4 == 0);
322 Amount /= 4;
324 bool isU6 = isImmU6(Amount);
325 if (!isU6 && !isImmU16(Amount)) {
329 << Amount << "\n"
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_emulate_loops.c | 53 float Amount;
119 float amount; local
156 amount = rc_get_constant_value(count_inst->C,
167 count_inst->Amount += amount;
174 count_inst->Amount -= amount;
232 count_inst.Amount = 0.0f;
272 if(count_inst.Amount == 0.0f){
275 DBG("Counter is increased by %f each iteration.\n", count_inst.Amount);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 249 // ... otherwise the amount to pop is *all* of the argument space,
435 // A certain amount of implicit contract is present here. The actual stack
612 int64_t Amount = MI->getOperand(0).getImm();
613 Amount = RoundUpToAlignment(Amount, Align);
614 if (!IsDestroy) Amount = -Amount;
624 assert(Amount > -0xfff && Amount < 0xfff && "call frame too large");
625 emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, Amount);
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 187 unsigned Amount;
313 return ShiftExtend.Amount == Log2_32(MemSize) || ShiftExtend.Amount == 0;
453 return is64Bit ? ShiftExtend.Amount <= 63 : ShiftExtend.Amount <= 31;
655 return ShiftExtend.Amount <= 4;
664 return !ShiftExtend.ImplicitAmount && ShiftExtend.Amount <= 4;
674 // Valid shift amount is 0, 8, 16 and 24.
675 return ShiftExtend.Amount % 8 == 0 && ShiftExtend.Amount <= 24
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /prebuilts/misc/common/icu4j/ |
| icu4j.jar | |
