/external/llvm/lib/Target/NVPTX/ |
NVPTXRegisterInfo.cpp | 105 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 108 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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/external/llvm/lib/Target/Sparc/ |
SparcRegisterInfo.cpp | 85 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 89 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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/external/chromium_org/third_party/opus/src/silk/ |
dec_API.c | 266 opus_int FrameIndex; 269 FrameIndex = channel_state[ 0 ].nFramesDecoded - n; 271 if( FrameIndex <= 0 ) { 274 condCoding = channel_state[ n ].LBRR_flags[ FrameIndex - 1 ] ? CODE_CONDITIONALLY : CODE_INDEPENDENTLY;
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/external/llvm/lib/Target/AArch64/ |
AArch64RegisterInfo.cpp | 106 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 107 bool IsCalleeSaveOp = FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI; 111 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
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/external/llvm/lib/Target/MSP430/ |
MSP430RegisterInfo.cpp | 114 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 117 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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MSP430ISelDAGToDAG.cpp | 43 int FrameIndex; 69 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'; 200 case ISD::FrameIndex: 204 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 262 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, 404 case ISD::FrameIndex: {
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MSP430ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsRegisterInfo.cpp | 185 // FrameIndex represent objects inside a abstract stack. 186 // We must replace FrameIndex with an stack/frame pointer 197 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 199 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 201 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 205 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
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/external/llvm/lib/Target/SystemZ/ |
SystemZRegisterInfo.cpp | 70 int FrameIndex = MI->getOperand(FIOperandNum).getIndex(); 72 int64_t Offset = (TFI->getFrameIndexOffset(MF, FrameIndex) +
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SystemZISelDAGToDAG.cpp | 441 if (Base->getOpcode() == ISD::FrameIndex) 538 else if (Base.getOpcode() == ISD::FrameIndex) { 539 // Lower a FrameIndex to a TargetFrameIndex. 540 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex(); 541 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 45 int FrameIndex; 68 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex)); 130 MIB.addFrameIndex(AM.Base.FrameIndex); 144 /// reference has base register as the FrameIndex offset until it is resolved.
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X86RegisterInfo.cpp | 468 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 474 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister()); 476 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); 483 // FrameIndex with base register with EBP. Add an offset to the offset. 491 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea(); 493 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
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/external/llvm/include/llvm/CodeGen/ |
RegisterScavenging.h | 45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {} 48 int FrameIndex; 136 if (I->FrameIndex == FI) 146 if (I->FrameIndex >= 0) 147 A.push_back(I->FrameIndex);
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ISDOpcodes.h | 62 GlobalAddress, GlobalTLSAddress, FrameIndex, [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonRegisterInfo.cpp | 127 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 133 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 112 int FrameIndex = FrameOp.getIndex(); 117 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 125 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
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/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 369 unsigned FrameIndex) const { 406 FrameIndex); 413 unsigned FrameIndex) const { 432 Reg), FrameIndex); 455 unsigned FrameIndex) const { 473 FrameIndex); 480 unsigned FrameIndex) const { 496 Reg), FrameIndex); 573 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 583 if (FPSI && FrameIndex == FPSI & [all...] |
/external/llvm/lib/CodeGen/ |
RegAllocFast.cpp | 623 int FrameIndex = getStackSpaceFor(VirtReg, RC); 626 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.cpp | 482 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 604 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 625 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 699 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 702 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 709 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
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ARMISelLowering.cpp | [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
DwarfDebug.h | 152 int FrameIndex; 157 FrameIndex(~0) {} 169 int getFrameIndex() const { return FrameIndex; } 170 void setFrameIndex(int FI) { FrameIndex = FI; }
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/external/llvm/lib/Target/R600/ |
R600ISelLowering.cpp | 90 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); 492 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); 804 unsigned FrameIndex = FIN->getIndex(); 805 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex); [all...] |