1 /** 2 * @file daemon/opd_ibs_macro.h 3 * AMD Instruction Based Sampling (IBS) related macro. 4 * 5 * @remark Copyright 2008-2010 OProfile authors 6 * @remark Read the file COPYING 7 * 8 * @author Jason Yeh <jason.yeh (at) amd.com> 9 * @author Paul Drongowski <paul.drongowski (at) amd.com> 10 * @author Suravee Suthikulpanit <suravee.suthikulpanit (at) amd.com> 11 * Copyright (c) 2008 Advanced Micro Devices, Inc. 12 */ 13 14 #ifndef OPD_IBS_MACRO_H 15 #define OPD_IBS_MACRO_H 16 17 /** 18 * The following defines are bit masks that are used to select 19 * IBS fetch event flags and values at the 20 * MSRC001_1030 IBS Fetch Control Register (IbsFetchCtl) 21 */ 22 #define FETCH_MASK_LATENCY 0x0000ffff 23 #define FETCH_MASK_COMPLETE 0x00040000 24 #define FETCH_MASK_IC_MISS 0x00080000 25 #define FETCH_MASK_PHY_ADDR 0x00100000 26 #define FETCH_MASK_PG_SIZE 0x00600000 27 #define FETCH_MASK_L1_MISS 0x00800000 28 #define FETCH_MASK_L2_MISS 0x01000000 29 #define FETCH_MASK_KILLED \ 30 (FETCH_MASK_L1_MISS|FETCH_MASK_L2_MISS|FETCH_MASK_PHY_ADDR|\ 31 FETCH_MASK_COMPLETE|FETCH_MASK_IC_MISS) 32 33 34 /** 35 * The following defines are bit masks that are used to select 36 * IBS op event flags and values at the MSR level. 37 */ 38 39 /* MSRC001_1035 IBS Op Data Register (IbsOpData) */ 40 #define BR_MASK_RETIRE 0x0000ffff 41 #define MASK_RIP_INVALID 0x00000040 42 #define BR_MASK_BRN_RET 0x00000020 43 #define BR_MASK_BRN_MISP 0x00000010 44 #define BR_MASK_BRN_TAKEN 0x00000008 45 #define BR_MASK_RETURN 0x00000004 46 #define BR_MASK_MISP_RETURN 0x00000002 47 #define BR_MASK_BRN_RESYNC 0x00000001 48 49 /* MSRC001_1036 IBS Op Data Register (IbsOpData2) */ 50 #define NB_MASK_L3_STATE 0x00000020 51 #define NB_MASK_REQ_DST_PROC 0x00000010 52 #define NB_MASK_REQ_DATA_SRC 0x00000007 53 54 /* MSRC001_1037 IBS Op Data Register (IbsOpData3) */ 55 #define DC_MASK_L2_HIT_1G 0x00080000 56 #define DC_MASK_PHY_ADDR_VALID 0x00040000 57 #define DC_MASK_LIN_ADDR_VALID 0x00020000 58 #define DC_MASK_MAB_HIT 0x00010000 59 #define DC_MASK_LOCKED_OP 0x00008000 60 #define DC_MASK_UC_MEM_ACCESS 0x00004000 61 #define DC_MASK_WC_MEM_ACCESS 0x00002000 62 #define DC_MASK_ST_TO_LD_CANCEL 0x00001000 63 #define DC_MASK_ST_TO_LD_FOR 0x00000800 64 #define DC_MASK_ST_BANK_CONFLICT 0x00000400 65 #define DC_MASK_LD_BANK_CONFLICT 0x00000200 66 #define DC_MASK_MISALIGN_ACCESS 0x00000100 67 #define DC_MASK_DC_MISS 0x00000080 68 #define DC_MASK_L2_HIT_2M 0x00000040 69 #define DC_MASK_L1_HIT_1G 0x00000020 70 #define DC_MASK_L1_HIT_2M 0x00000010 71 #define DC_MASK_L2_TLB_MISS 0x00000008 72 #define DC_MASK_L1_TLB_MISS 0x00000004 73 #define DC_MASK_STORE_OP 0x00000002 74 #define DC_MASK_LOAD_OP 0x00000001 75 76 77 /** 78 * IBS derived events: 79 * 80 * IBS derived events are identified by event select values which are 81 * similar to the event select values that identify performance monitoring 82 * counter (PMC) events. Event select values for IBS derived events begin 83 * at 0xf000. 84 * 85 * The definitions in this file *must* match definitions 86 * of IBS derived events. More information 87 * about IBS derived events is given in the Software Oprimization 88 * Guide. 89 */ 90 91 /** 92 * The following defines associate a 16-bit select value with an IBS 93 * derived fetch event. 94 */ 95 #define DE_IBS_FETCH_ALL 0xf000 96 #define DE_IBS_FETCH_KILLED 0xf001 97 #define DE_IBS_FETCH_ATTEMPTED 0xf002 98 #define DE_IBS_FETCH_COMPLETED 0xf003 99 #define DE_IBS_FETCH_ABORTED 0xf004 100 #define DE_IBS_L1_ITLB_HIT 0xf005 101 #define DE_IBS_ITLB_L1M_L2H 0xf006 102 #define DE_IBS_ITLB_L1M_L2M 0xf007 103 #define DE_IBS_IC_MISS 0xf008 104 #define DE_IBS_IC_HIT 0xf009 105 #define DE_IBS_FETCH_4K_PAGE 0xf00a 106 #define DE_IBS_FETCH_2M_PAGE 0xf00b 107 #define DE_IBS_FETCH_1G_PAGE 0xf00c 108 #define DE_IBS_FETCH_XX_PAGE 0xf00d 109 #define DE_IBS_FETCH_LATENCY 0xf00e 110 111 #define IBS_FETCH_BASE 0xf000 112 #define IBS_FETCH_END 0xf00e 113 #define IBS_FETCH_MAX (IBS_FETCH_END - IBS_FETCH_BASE + 1) 114 #define IS_IBS_FETCH(x) (IBS_FETCH_BASE <= x && x <= IBS_FETCH_END) 115 #define IBS_FETCH_OFFSET(x) (x - IBS_FETCH_BASE) 116 #define CHECK_FETCH_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_FETCH_OFFSET(x))) 117 118 119 /** 120 * The following defines associate a 16-bit select value with an IBS 121 * derived branch/return macro-op event. 122 */ 123 #define DE_IBS_OP_ALL 0xf100 124 #define DE_IBS_OP_TAG_TO_RETIRE 0xf101 125 #define DE_IBS_OP_COMP_TO_RETIRE 0xf102 126 #define DE_IBS_BRANCH_RETIRED 0xf103 127 #define DE_IBS_BRANCH_MISP 0xf104 128 #define DE_IBS_BRANCH_TAKEN 0xf105 129 #define DE_IBS_BRANCH_MISP_TAKEN 0xf106 130 #define DE_IBS_RETURN 0xf107 131 #define DE_IBS_RETURN_MISP 0xf108 132 #define DE_IBS_RESYNC 0xf109 133 134 #define IBS_OP_BASE 0xf100 135 #define IBS_OP_END 0xf109 136 #define IBS_OP_MAX (IBS_OP_END - IBS_OP_BASE + 1) 137 #define IS_IBS_OP(x) (IBS_OP_BASE <= x && x <= IBS_OP_END) 138 #define IBS_OP_OFFSET(x) (x - IBS_OP_BASE) 139 #define CHECK_OP_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_OP_OFFSET(x))) 140 141 142 /** 143 * The following defines associate a 16-bit select value with an IBS 144 * derived load/store event. 145 */ 146 #define DE_IBS_LS_ALL_OP 0xf200 147 #define DE_IBS_LS_LOAD_OP 0xf201 148 #define DE_IBS_LS_STORE_OP 0xf202 149 #define DE_IBS_LS_DTLB_L1H 0xf203 150 #define DE_IBS_LS_DTLB_L1M_L2H 0xf204 151 #define DE_IBS_LS_DTLB_L1M_L2M 0xf205 152 #define DE_IBS_LS_DC_MISS 0xf206 153 #define DE_IBS_LS_DC_HIT 0xf207 154 #define DE_IBS_LS_MISALIGNED 0xf208 155 #define DE_IBS_LS_BNK_CONF_LOAD 0xf209 156 #define DE_IBS_LS_BNK_CONF_STORE 0xf20a 157 #define DE_IBS_LS_STL_FORWARDED 0xf20b 158 #define DE_IBS_LS_STL_CANCELLED 0xf20c 159 #define DE_IBS_LS_UC_MEM_ACCESS 0xf20d 160 #define DE_IBS_LS_WC_MEM_ACCESS 0xf20e 161 #define DE_IBS_LS_LOCKED_OP 0xf20f 162 #define DE_IBS_LS_MAB_HIT 0xf210 163 #define DE_IBS_LS_L1_DTLB_4K 0xf211 164 #define DE_IBS_LS_L1_DTLB_2M 0xf212 165 #define DE_IBS_LS_L1_DTLB_1G 0xf213 166 #define DE_IBS_LS_L1_DTLB_RES 0xf214 167 #define DE_IBS_LS_L2_DTLB_4K 0xf215 168 #define DE_IBS_LS_L2_DTLB_2M 0xf216 169 #define DE_IBS_LS_L2_DTLB_1G 0xf217 170 #define DE_IBS_LS_L2_DTLB_RES2 0xf218 171 #define DE_IBS_LS_DC_LOAD_LAT 0xf219 172 173 #define IBS_OP_LS_BASE 0xf200 174 #define IBS_OP_LS_END 0xf219 175 #define IBS_OP_LS_MAX (IBS_OP_LS_END - IBS_OP_LS_BASE + 1) 176 #define IS_IBS_OP_LS(x) (IBS_OP_LS_BASE <= x && x <= IBS_OP_LS_END) 177 #define IBS_OP_LS_OFFSET(x) (x - IBS_OP_LS_BASE) 178 #define CHECK_OP_LS_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_OP_LS_OFFSET(x))) 179 180 181 /** 182 * The following defines associate a 16-bit select value with an IBS 183 * derived Northbridge (NB) event. 184 */ 185 #define DE_IBS_NB_LOCAL 0xf240 186 #define DE_IBS_NB_REMOTE 0xf241 187 #define DE_IBS_NB_LOCAL_L3 0xf242 188 #define DE_IBS_NB_LOCAL_CACHE 0xf243 189 #define DE_IBS_NB_REMOTE_CACHE 0xf244 190 #define DE_IBS_NB_LOCAL_DRAM 0xf245 191 #define DE_IBS_NB_REMOTE_DRAM 0xf246 192 #define DE_IBS_NB_LOCAL_OTHER 0xf247 193 #define DE_IBS_NB_REMOTE_OTHER 0xf248 194 #define DE_IBS_NB_CACHE_STATE_M 0xf249 195 #define DE_IBS_NB_CACHE_STATE_O 0xf24a 196 #define DE_IBS_NB_LOCAL_LATENCY 0xf24b 197 #define DE_IBS_NB_REMOTE_LATENCY 0xf24c 198 199 #define IBS_OP_NB_BASE 0xf240 200 #define IBS_OP_NB_END 0xf24c 201 #define IBS_OP_NB_MAX (IBS_OP_NB_END - IBS_OP_NB_BASE + 1) 202 #define IS_IBS_OP_NB(x) (IBS_OP_NB_BASE <= x && x <= IBS_OP_NB_END) 203 #define IBS_OP_NB_OFFSET(x) (x - IBS_OP_NB_BASE) 204 #define CHECK_OP_NB_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_OP_NB_OFFSET(x))) 205 206 207 #define OP_MAX_IBS_COUNTERS (IBS_FETCH_MAX + IBS_OP_MAX + IBS_OP_LS_MAX + IBS_OP_NB_MAX) 208 209 210 /** 211 * These macro decodes IBS hardware-level event flags and fields. 212 * Translation results are either zero (false) or non-zero (true), except 213 * the fetch latency, which is a 16-bit cycle count, and the fetch page size 214 * field, which is a 2-bit unsigned integer. 215 */ 216 217 /** Bits 47:32 IbsFetchLat: instruction fetch latency */ 218 #define IBS_FETCH_FETCH_LATENCY(x) ((unsigned short)(x->ibs_fetch_ctl_high & FETCH_MASK_LATENCY)) 219 220 /** Bit 50 IbsFetchComp: instruction fetch complete. */ 221 #define IBS_FETCH_FETCH_COMPLETION(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_COMPLETE) != 0) 222 223 /** Bit 51 IbsIcMiss: instruction cache miss. */ 224 #define IBS_FETCH_INST_CACHE_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_IC_MISS) != 0) 225 226 /** Bit 52 IbsPhyAddrValid: instruction fetch physical address valid. */ 227 #define IBS_FETCH_PHYS_ADDR_VALID(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_PHY_ADDR) != 0) 228 229 enum IBSL1PAGESIZE { 230 L1TLB4K = 0, 231 L1TLB2M, 232 L1TLB1G, 233 L1TLB_INVALID 234 }; 235 236 /** Bits 54:53 IbsL1TlbPgSz: instruction cache L1TLB page size. */ 237 #define IBS_FETCH_TLB_PAGE_SIZE(x) ((unsigned short)((x->ibs_fetch_ctl_high >> 21) & 0x3)) 238 #define IBS_FETCH_TLB_PAGE_SIZE_4K(x) (IBS_FETCH_TLB_PAGE_SIZE(x) == L1TLB4K) 239 #define IBS_FETCH_TLB_PAGE_SIZE_2M(x) (IBS_FETCH_TLB_PAGE_SIZE(x) == L1TLB2M) 240 #define IBS_FETCH_TLB_PAGE_SIZE_1G(x) (IBS_FETCH_TLB_PAGE_SIZE(x) == L1TLB1G) 241 242 /** Bit 55 IbsL1TlbMiss: instruction cache L1TLB miss. */ 243 #define IBS_FETCH_M_L1_TLB_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_L1_MISS) != 0) 244 245 /** Bit 56 IbsL2TlbMiss: instruction cache L2TLB miss. */ 246 #define IBS_FETCH_L2_TLB_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_L2_MISS) != 0) 247 248 /** A fetch is a killed fetch if all the masked bits are clear */ 249 #define IBS_FETCH_KILLED(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_KILLED) == 0) 250 251 #define IBS_FETCH_INST_CACHE_HIT(x) (IBS_FETCH_FETCH_COMPLETION(x) && !IBS_FETCH_INST_CACHE_MISS(x)) 252 253 #define IBS_FETCH_L1_TLB_HIT(x) (!IBS_FETCH_M_L1_TLB_MISS(x) && IBS_FETCH_PHYS_ADDR_VALID(x)) 254 255 #define IBS_FETCH_ITLB_L1M_L2H(x) (IBS_FETCH_M_L1_TLB_MISS(x) && !IBS_FETCH_L2_TLB_MISS(x)) 256 257 #define IBS_FETCH_ITLB_L1M_L2M(x) (IBS_FETCH_M_L1_TLB_MISS(x) && IBS_FETCH_L2_TLB_MISS(x)) 258 259 260 /** 261 * These macros translates IBS op event data from its hardware-level 262 * representation .It hides the MSR layout of IBS op data. 263 */ 264 265 /** 266 * MSRC001_1035 IBS OP Data Register (IbsOpData) 267 * 268 * 15:0 IbsCompToRetCtr: macro-op completion to retire count 269 */ 270 #define IBS_OP_COM_TO_RETIRE_CYCLES(x) ((unsigned short)(x->ibs_op_data1_low & BR_MASK_RETIRE)) 271 272 /** 31:16 tag_to_retire_cycles : macro-op tag to retire count. */ 273 #define IBS_OP_TAG_TO_RETIRE_CYCLES(x) ((unsigned short)((x->ibs_op_data1_low >> 16) & BR_MASK_RETIRE)) 274 275 /** 32 op_branch_resync : resync macro-op. */ 276 #define IBS_OP_BRANCH_RESYNC(x) ((x->ibs_op_data1_high & BR_MASK_BRN_RESYNC) != 0) 277 278 /** 33 op_mispredict_return : mispredicted return macro-op. */ 279 #define IBS_OP_MISPREDICT_RETURN(x) ((x->ibs_op_data1_high & BR_MASK_MISP_RETURN) != 0) 280 281 /** 34 IbsOpReturn: return macro-op. */ 282 #define IBS_OP_RETURN(x) ((x->ibs_op_data1_high & BR_MASK_RETURN) != 0) 283 284 /** 35 IbsOpBrnTaken: taken branch macro-op. */ 285 #define IBS_OP_BRANCH_TAKEN(x) ((x->ibs_op_data1_high & BR_MASK_BRN_TAKEN) != 0) 286 287 /** 36 IbsOpBrnMisp: mispredicted branch macro-op. */ 288 #define IBS_OP_BRANCH_MISPREDICT(x) ((x->ibs_op_data1_high & BR_MASK_BRN_MISP) != 0) 289 290 /** 37 IbsOpBrnRet: branch macro-op retired. */ 291 #define IBS_OP_BRANCH_RETIRED(x) ((x->ibs_op_data1_high & BR_MASK_BRN_RET) != 0) 292 293 /** 38 IbsRipInvalid: RIP invalid. */ 294 #define IBS_OP_RIP_INVALID(x) ((x->ibs_op_data1_high & MASK_RIP_INVALID) != 0) 295 296 /** 297 * MSRC001_1036 IBS Op Data 2 Register (IbsOpData2) 298 * 299 * 5 NbIbsReqCacheHitSt: IBS L3 cache state 300 */ 301 #define IBS_OP_NB_IBS_CACHE_HIT_ST(x) ((x->ibs_op_data2_low & NB_MASK_L3_STATE) != 0) 302 303 /** 4 NbIbsReqDstProc: IBS request destination processor */ 304 #define IBS_OP_NB_IBS_REQ_DST_PROC(x) ((x->ibs_op_data2_low & NB_MASK_REQ_DST_PROC) != 0) 305 306 /** 2:0 NbIbsReqSrc: Northbridge IBS request data source */ 307 #define IBS_OP_NB_IBS_REQ_SRC(x) ((unsigned char)(x->ibs_op_data2_low & NB_MASK_REQ_DATA_SRC)) 308 309 #define IBS_OP_NB_IBS_REQ_SRC_01(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x01) 310 311 #define IBS_OP_NB_IBS_REQ_SRC_02(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x02) 312 313 #define IBS_OP_NB_IBS_REQ_SRC_03(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x03) 314 315 #define IBS_OP_NB_IBS_REQ_SRC_07(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x07) 316 317 /** 318 * MSRC001_1037 IBS Op Data3 Register 319 * 320 * Bits 47:32 IbsDcMissLat 321 */ 322 #define IBS_OP_DC_MISS_LATENCY(x) ((unsigned short)(x->ibs_op_data3_high & 0xffff)) 323 324 /** 0 IbsLdOp: Load op */ 325 #define IBS_OP_IBS_LD_OP(x) ((x->ibs_op_data3_low & DC_MASK_LOAD_OP) != 0) 326 327 /** 1 IbsStOp: Store op */ 328 #define IBS_OP_IBS_ST_OP(x) ((x->ibs_op_data3_low & DC_MASK_STORE_OP) != 0) 329 330 /** 2 ibs_dc_l1_tlb_miss: Data cache L1TLB miss */ 331 #define IBS_OP_IBS_DC_L1_TLB_MISS(x) ((x->ibs_op_data3_low & DC_MASK_L1_TLB_MISS) != 0) 332 333 /** 3 ibs_dc_l2_tlb_miss: Data cache L2TLB miss */ 334 #define IBS_OP_IBS_DC_L2_TLB_MISS(x) ((x->ibs_op_data3_low & DC_MASK_L2_TLB_MISS) != 0) 335 336 /** 4 IbsDcL1tlbHit2M: Data cache L1TLB hit in 2M page */ 337 #define IBS_OP_IBS_DC_L1_TLB_HIT_2MB(x) ((x->ibs_op_data3_low & DC_MASK_L1_HIT_2M) != 0) 338 339 /** 5 ibs_dc_l1_tlb_hit_1gb: Data cache L1TLB hit in 1G page */ 340 #define IBS_OP_IBS_DC_L1_TLB_HIT_1GB(x) ((x->ibs_op_data3_low & DC_MASK_L1_HIT_1G) != 0) 341 342 /** 6 ibs_dc_l2_tlb_hit_2mb: Data cache L2TLB hit in 2M page */ 343 #define IBS_OP_IBS_DC_L2_TLB_HIT_2MB(x) ((x->ibs_op_data3_low & DC_MASK_L2_HIT_2M) != 0) 344 345 /** 7 ibs_dc_miss: Data cache miss */ 346 #define IBS_OP_IBS_DC_MISS(x) ((x->ibs_op_data3_low & DC_MASK_DC_MISS) != 0) 347 348 /** 8 ibs_dc_miss_acc: Misaligned access */ 349 #define IBS_OP_IBS_DC_MISS_ACC(x) ((x->ibs_op_data3_low & DC_MASK_MISALIGN_ACCESS) != 0) 350 351 /** 9 ibs_dc_ld_bnk_con: Bank conflict on load operation */ 352 #define IBS_OP_IBS_DC_LD_BNK_CON(x) ((x->ibs_op_data3_low & DC_MASK_LD_BANK_CONFLICT) != 0) 353 354 /** 10 ibs_dc_st_bnk_con: Bank conflict on store operation */ 355 #define IBS_OP_IBS_DC_ST_BNK_CON(x) ((x->ibs_op_data3_low & DC_MASK_ST_BANK_CONFLICT) != 0) 356 357 /** 11 ibs_dc_st_to_ld_fwd : Data forwarded from store to load operation */ 358 #define IBS_OP_IBS_DC_ST_TO_LD_FWD(x) ((x->ibs_op_data3_low & DC_MASK_ST_TO_LD_FOR) != 0) 359 360 /** 12 ibs_dc_st_to_ld_can: Data forwarding from store to load operation cancelled */ 361 #define IBS_OP_IBS_DC_ST_TO_LD_CAN(x) ((x->ibs_op_data3_low & DC_MASK_ST_TO_LD_CANCEL) != 0) 362 363 /** 13 ibs_dc_wc_mem_acc : WC memory access */ 364 #define IBS_OP_IBS_DC_WC_MEM_ACC(x) ((x->ibs_op_data3_low & DC_MASK_WC_MEM_ACCESS) != 0) 365 366 /** 14 ibs_dc_uc_mem_acc : UC memory access */ 367 #define IBS_OP_IBS_DC_UC_MEM_ACC(x) ((x->ibs_op_data3_low & DC_MASK_UC_MEM_ACCESS) != 0) 368 369 /** 15 ibs_locked_op: Locked operation */ 370 #define IBS_OP_IBS_LOCKED_OP(x) ((x->ibs_op_data3_low & DC_MASK_LOCKED_OP) != 0) 371 372 /** 16 ibs_dc_mab_hit : MAB hit */ 373 #define IBS_OP_IBS_DC_MAB_HIT(x) ((x->ibs_op_data3_low & DC_MASK_MAB_HIT) != 0) 374 375 /** 17 IbsDcLinAddrValid: Data cache linear address valid */ 376 #define IBS_OP_IBS_DC_LIN_ADDR_VALID(x) ((x->ibs_op_data3_low & DC_MASK_LIN_ADDR_VALID) != 0) 377 378 /** 18 ibs_dc_phy_addr_valid: Data cache physical address valid */ 379 #define IBS_OP_IBS_DC_PHY_ADDR_VALID(x) ((x->ibs_op_data3_low & DC_MASK_PHY_ADDR_VALID) != 0) 380 381 /** 19 ibs_dc_l2_tlb_hit_1gb: Data cache L2TLB hit in 1G page */ 382 #define IBS_OP_IBS_DC_L2_TLB_HIT_1GB(x) ((x->ibs_op_data3_low & DC_MASK_L2_HIT_1G) != 0) 383 384 385 /** 386 * Aggregate the IBS derived event. Increase the 387 * derived event count by one. 388 */ 389 #define AGG_IBS_EVENT(EV) opd_log_ibs_event(EV, trans) 390 391 /** 392 * Aggregate the IBS latency/cycle counts. Increase the 393 * derived event count by the specified count value. 394 */ 395 #define AGG_IBS_COUNT(EV, COUNT) opd_log_ibs_count(EV, trans, COUNT) 396 397 #endif /*OPD_IBS_MACRO_H*/ 398
